AD9281ParameterSymbolMinTypMaxUnitsCondition DYNAMIC PERFORMANCE (SE)1 Signal-to-Noise and Distortion SINAD f = 3.58 MHz 47.2 dB Signal-to-Noise SNR f = 3.58 MHz 48 dB Total Harmonic Distortion THD f = 3.58 MHz –55 dB Spurious Free Dynamic Range SFDR f = 3.58 MHz –58 dB DIGITAL INPUTS High Input Voltage VIH 2.4 V Low Input Voltage VIL 0.3 V DC Leakage Current I ± IN 6 µA Input Capacitance CIN 2 pF LOGIC OUTPUT (with DVDD = 3 V) High Level Output Voltage (IOH = 50 µA) VOH 2.88 V Low Level Output Voltage (IOL = 1.5 mA) VOL 0.095 V LOGIC OUTPUT (with DVDD = 5 V) High Level Output Voltage (IOH = 50 µA) VOH 4.5 V Low Level Output Voltage (IOL = 1.5 mA) VOL 0.4 V Data Valid Delay tOD 11 ns MUX Select Delay tMD 7 ns Data Enable Delay tED 13 ns CL = 20 pF. Output Level to 90% of Final Value Data High-Z Delay tDHZ 13 ns CLOCKING Clock Pulsewidth High tCH 16.9 ns Clock Pulsewidth Low tCL 16.9 ns Pipeline Latency 3.0 Cycles NOTES 1SE is single ended input, REFT = 1.5 V, REFB = –0.5 V. 2AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V. 3IMD referred to larger of two input signals. Specifications subject to change without notice. tODCLOCKINPUTADC SAMPLEADC SAMPLEADC SAMPLEADC SAMPLEADC SAMPLE#1#2#3#4#5SELECTQ CHANNELtI CHANNELINPUTMDOUTPUT ENABLEDOUTPUT ENABLEDSAMPLE #1-1SAMPLE #1SAMPLE #2Q CHANNELQ CHANNELQ CHANNELOUTPUTOUTPUTOUTPUTDATASAMPLE #1-3SAMPLE #1-2OUTPUTQ CHANNELQ CHANNELOUTPUTOUTPUTSAMPLE #1-1SAMPLE #1I CHANNELI CHANNELOUTPUTOUTPUT Figure 1. ADC Timing REV. F –3–