Datasheet AD9281 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | Dual Channel 8-Bit Resolution CMOS ADC |
| 页数 / 页 | 16 / 9 — AD9281. 10.0. FUND. 0.0. –10.0 –20.0. –30.0. –40.0. –50.0. SNR – dB … |
| 修订版 | F |
| 文件格式/大小 | PDF / 415 Kb |
| 文件语言 | 英语 |
AD9281. 10.0. FUND. 0.0. –10.0 –20.0. –30.0. –40.0. –50.0. SNR – dB –60.0. 5TH. 2ND. 3RD. 6TH. –70.0. 7TH. 9TH. 4TH. 8TH. –80.0 –90.0. –100.0. –110.0
该数据表的模型线
文件文字版本
AD9281 10.0
converter to readily accommodate either single-ended or differ-
FUND 0.0
ential input signals. This differential structure makes the part capable of accommodating a wide range of input signals.
–10.0 –20.0
The AD9281 also includes an on-chip bandgap reference and
–30.0
reference buffer. The reference buffer shifts the ground-referred
–40.0
reference to levels more suitable for use by the internal circuits of the converter. Both converters share the same reference and
–50.0
reference buffer. This scheme provides for the best possible gain
SNR – dB –60.0 5TH 2ND 3RD 6TH
match between the converters while simultaneously minimizing
–70.0 7TH 9TH 4TH 8TH
the channel-to-channel crosstalk.
–80.0 –90.0
Each A/D converter has its own output latch, which updates on the rising edge of the input clock. A logic multiplexer, con-
–100.0
trolled through the SELECT pin, determines which channel is
–110.0 0.0E+0 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.0E+6 14.0E+6
passed to the digital output pins. The output drivers have their own supply, allowing the part to be interfaced to a variety of Figure 15a. Simultaneous Operation of I and Q Channels logic families. The outputs can be placed in a high impedance state using the CHIP SELECT pin.
10.0 FUND 0.0
The AD9281 has great flexibility in its supply voltage. The
–10.0
analog and digital supplies may be operated from 2.7 V to 5.5 V, independently of one another.
–20.0 –30.0 ANALOG INPUT –40.0
Figure 16 shows an equivalent circuit structure for the analog
–50.0
input of one of the A/D converters. PMOS source-followers
SNR – dB –60.0 5TH
buffer the analog input pins from the charge kickback problems
–70.0 2ND 3RD 7TH 8TH 6TH
normally associated with switched capacitor ADC input struc-
–80.0 4TH
tures. This produces a very high input impedance on the part,
–90.0
allowing it to be effectively driven from high impedance sources.
–100.0
This means that the AD9281 could even be driven directly by a
–110.0
passive antialias filter.
0.0E+0 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.0E+6 14.0E+6
Figure 15b. Simultaneous Operation of I and Q Channels
IINA BUFFER OUTPUT THEORY OF OPERATION WORD ADC
The AD9281 integrates two A/D converters, two analog input
CORE SHA
buffers, an internal reference and reference buffer, and an out-
+FS –FS LIMIT LIMIT
put multiplexer. For clarity, this data sheet refers to the two
IINB BUFFER
converters as “I” and “Q.” The two A/D converters simulta-
+FS LIMIT = –FS LIMIT =
neously sample their respective inputs on the rising edge of the
VREF +VREF/2 VREF –VREF/2
input clock. The two converters distribute the conversion opera- tion over several smaller A/D sub-blocks, refining the conversion
VREF
with progressively higher accuracy as it passes the result from stage to stage. As a consequence of the distributed conversion, Figure 16. Equivalent Circuit for AD9281 Analog Inputs each converter requires a small fraction of the 256 comparators The source followers inside the buffers also provide a level-shift used in a traditional flash-type 8-bit ADC. A sample-and-hold function of approximately 1 V, allowing the AD9281 to accept function within each of the stages permits the first stage to oper- inputs at or below ground. One consequence of this structure is ate on a new input sample while the following stages continue to that distortion will result if the analog input comes within 1.4 V process previous samples. This results in a “pipeline processing” of the positive supply. For optimum high frequency distortion latency of three clock periods between when an input sample is performance, the analog input signal should be centered accord- taken and when the corresponding ADC output is updated into ing to Figure 27. the output registers. The capacitance load of the analog input pin is 4 pF to the The AD9281 integrates input buffer amplifiers to drive the analog supplies (AVSS, AVDD). analog inputs of the converters. In most applications, these input amplifiers eliminate the need for external op amps for the Full-scale setpoints may be calculated according to the following input signals. The input structure is fully differential, but the algorithm (VREF may be internally or externally generated): SHA common-mode response has been designed to allow the –FS = VREF – (VREF/2) +FS = VREF + (VREF/2) VSPAN = VREF –8– REV. F
converter to readily accommodate either single-ended or differ-
FUND 0.0
ential input signals. This differential structure makes the part capable of accommodating a wide range of input signals.
–10.0 –20.0
The AD9281 also includes an on-chip bandgap reference and
–30.0
reference buffer. The reference buffer shifts the ground-referred
–40.0
reference to levels more suitable for use by the internal circuits of the converter. Both converters share the same reference and
–50.0
reference buffer. This scheme provides for the best possible gain
SNR – dB –60.0 5TH 2ND 3RD 6TH
match between the converters while simultaneously minimizing
–70.0 7TH 9TH 4TH 8TH
the channel-to-channel crosstalk.
–80.0 –90.0
Each A/D converter has its own output latch, which updates on the rising edge of the input clock. A logic multiplexer, con-
–100.0
trolled through the SELECT pin, determines which channel is
–110.0 0.0E+0 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.0E+6 14.0E+6
passed to the digital output pins. The output drivers have their own supply, allowing the part to be interfaced to a variety of Figure 15a. Simultaneous Operation of I and Q Channels logic families. The outputs can be placed in a high impedance state using the CHIP SELECT pin.
10.0 FUND 0.0
The AD9281 has great flexibility in its supply voltage. The
–10.0
analog and digital supplies may be operated from 2.7 V to 5.5 V, independently of one another.
–20.0 –30.0 ANALOG INPUT –40.0
Figure 16 shows an equivalent circuit structure for the analog
–50.0
input of one of the A/D converters. PMOS source-followers
SNR – dB –60.0 5TH
buffer the analog input pins from the charge kickback problems
–70.0 2ND 3RD 7TH 8TH 6TH
normally associated with switched capacitor ADC input struc-
–80.0 4TH
tures. This produces a very high input impedance on the part,
–90.0
allowing it to be effectively driven from high impedance sources.
–100.0
This means that the AD9281 could even be driven directly by a
–110.0
passive antialias filter.
0.0E+0 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.0E+6 14.0E+6
Figure 15b. Simultaneous Operation of I and Q Channels
IINA BUFFER OUTPUT THEORY OF OPERATION WORD ADC
The AD9281 integrates two A/D converters, two analog input
CORE SHA
buffers, an internal reference and reference buffer, and an out-
+FS –FS LIMIT LIMIT
put multiplexer. For clarity, this data sheet refers to the two
IINB BUFFER
converters as “I” and “Q.” The two A/D converters simulta-
+FS LIMIT = –FS LIMIT =
neously sample their respective inputs on the rising edge of the
VREF +VREF/2 VREF –VREF/2
input clock. The two converters distribute the conversion opera- tion over several smaller A/D sub-blocks, refining the conversion
VREF
with progressively higher accuracy as it passes the result from stage to stage. As a consequence of the distributed conversion, Figure 16. Equivalent Circuit for AD9281 Analog Inputs each converter requires a small fraction of the 256 comparators The source followers inside the buffers also provide a level-shift used in a traditional flash-type 8-bit ADC. A sample-and-hold function of approximately 1 V, allowing the AD9281 to accept function within each of the stages permits the first stage to oper- inputs at or below ground. One consequence of this structure is ate on a new input sample while the following stages continue to that distortion will result if the analog input comes within 1.4 V process previous samples. This results in a “pipeline processing” of the positive supply. For optimum high frequency distortion latency of three clock periods between when an input sample is performance, the analog input signal should be centered accord- taken and when the corresponding ADC output is updated into ing to Figure 27. the output registers. The capacitance load of the analog input pin is 4 pF to the The AD9281 integrates input buffer amplifiers to drive the analog supplies (AVSS, AVDD). analog inputs of the converters. In most applications, these input amplifiers eliminate the need for external op amps for the Full-scale setpoints may be calculated according to the following input signals. The input structure is fully differential, but the algorithm (VREF may be internally or externally generated): SHA common-mode response has been designed to allow the –FS = VREF – (VREF/2) +FS = VREF + (VREF/2) VSPAN = VREF –8– REV. F