Datasheet AD9260 (Analog Devices) - 9
制造商 | Analog Devices |
描述 | 16-Bit High Speed Oversampled A/D Converter |
页数 / 页 | 45 / 9 — AD9260. Table 5. Integer Filter Coefficients for First Stage. Table 7. … |
修订版 | C |
文件格式/大小 | PDF / 1.1 Mb |
文件语言 | 英语 |
AD9260. Table 5. Integer Filter Coefficients for First Stage. Table 7. Integer Filter Coefficients for Third Stage
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AD9260 Table 5. Integer Filter Coefficients for First Stage Table 7. Integer Filter Coefficients for Third Stage Decimation Filter (23-Tap Half-Band FIR Filter) Decimation Filter (107-Tap Half-Band FIR Filter) Lower Coefficient Upper Coefficient Integer Value Lower Coefficient Upper Coefficient Integer Value
H(1) H(23) –1 H(1) H(107) –1 H(2) H(22) 0 H(2) H(106) 0 H(3) H(21) 13 H(3) H(105) 2 H(4) H(20) 0 H(4) H(104) 0 H(5) H(19) –66 H(5) H(103) –2 H(6) H(18) 0 H(6) H(102) 0 H(7) H(17) 224 H(7) H(101) 3 H(8) H(16) 0 H(8) H(100) 0 H(9) H(15) –642 H(9) H(99) –3 H(10) H(14) 0 H(10) H(98) 0 H(11) H(13) 2496 H(11) H(97) 1 H(12) 4048 H(12) H(96) 0 H(13) H(95) 3 H(14) H(94) 0
Table 6. Integer Filter Coefficients for Second Stage
H(15) H(93) –12
Decimation Filter (43-Tap Half-Band FIR Filter)
H(16) H(92) 0
Lower Coefficient Upper Coefficient Integer Value
H(17) H(91) 27 H(1) H(43) 3 H(18) H(90) 0 H(2) H(42) 0 H(19) H(89) –50 H(3) H(41) –12 H(20) H(88) 0 H(4) H(40) 0 H(21) H(87) 85 H(5) H(39) 35 H(22) H(86) 0 H(6) H(38) 0 H(23) H(85) –135 H(7) H(37) –83 H(24) H(84) 0 H(8) H(36) 0 H(25) H(83) 204 H(9) H(35) 172 H(26) H(82) 0 H(10) H(34) 0 H(27) H(81) –297 H(11) H(33) –324 H(28) H(80) 0 H(12) H(32) 0 H(29) H(79) 420 H(13) H(31) 572 H(30) H(78) 0 H(14) H(30) 0 H(31) H(77) –579 H(15) H(29) –976 H(32) H(76) 0 H(16) H(28) 0 H(33) H(75) 784 H(17) H(27) 1680 H(34) H(74) 0 H(18) H(26) 0 H(35) H(73) –1044 H(19) H(25) –3204 H(36) H(72) 0 H(20) H(24) 0 H(37) H(71) 1376 H(21) H(23) 10274 H(38) H(70) 0 H(22) 16274 H(39) H(69) –1797 H(40) H(68) 0
NOTE:
The composite filter undecimated coefficients (i.e., H(41) H(67) 2344 impulse response) in the 4× decimation mode can be H(42) H(66) 0 determined by convolving the first stage filter taps with a H(43) H(65) –3072 “zero stuffed” version of the second stage filter taps (i.e., insert H(44) H(64) 0 one zero between samples). Similarly, the composite filter H(45) H(63) 4089 coefficients in the 8× decimation mode can be determined by H(46) H(62) 0 convolving the taps of the composite 4× decimation mode (as H(47) H(61) –5624 previously determined) with a “zero stuffed” version of the third H(48) H(60) 0 H(49) H(59) 8280 stage filter taps (i.e., insert three zeros between samples). H(50) H(58) 0 H(51) H(57) –14268 H(52) H(56) 0 H(53) H(55) 43520 H(54) 68508 Rev. C | Page 8 of 44 Document Outline FEATURES PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS CLOCK INPUT FREQUENCY RANGE DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL FILTER CHARACTERISTICS DIGITAL FILTER CHARACTERISTICS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION TERMINOLOGY PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TYPICAL AC CHARACTERIZATION CURVES VS. DECIMATION MODE TYPICAL AC CHARACTERIZATION CURVES FOR 8× MODE TYPICAL AC CHARACTERIZATION CURVES FOR 4× MODE TYPICAL AC CHARACTERIZATION CURVES FOR 2× MODE TYPICAL AC CHARACTERIZATION CURVES FOR 1× MODE TYPICAL AC CHARACTERIZATION CURVES ADDITIONAL AC CHARACTERIZATION CURVES THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW INPUT SPAN INPUT COMPLIANCE RANGE ANALOG INPUT OPERATION DRIVING THE INPUT Transient Response Input Driver Considerations Single-Ended-to-Differential Op Amp Driver Common-Mode Level REFERENCE OPERATION DIGITAL INPUTS AND OUTPUTS DIGITAL OUTPUTS CS and Read Pins DAV Pin RESET Pin OTR Pin MODE OPERATION BIAS PIN OPERATION POWER DISSIPATION CONSIDERATIONS DIGITAL OUTPUT DRIVER CONSIDERATIONS (DRVDD) Clock Input and Considerations GROUNDING AND DECOUPLING Analog and Digital Grounding Analog and Digital Supply Decoupling EVALUATION BOARD GENERAL DESCRIPTION FEATURES AND USER CONTROLS Jumper Controlled Mode/OSR Selection Selectable Power Bias Data Interfacing Controls Buffered Output Data Jumper Controlled Reference Source Flexible DC or AC Coupled External Clock Inputs Flexible Input Signal Configuration Circuitry Selecting Single or Dual Signal Input Selectable Input Signal Common-Mode Level Source SHIPMENT CONFIGURATION QUICK SETUP APPLICATION INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE