Datasheet AD9201 (Analog Devices) - 9

AD9201 10
The AD9201 also includes an on-chip bandgap reference and
FUND 0
reference buffer. The reference buffer shifts the ground-referred
–10
reference to levels more suitable for use by the internal circuits
–20
of the converter. Both converters share the same reference and
–30
reference buffer. This scheme provides for the best possible gain
–40
match between the converters while simultaneously minimizing
–50
the channel-to-channel crosstalk. (See Figure 16.)
–60
Each A/D converter has its own output latch, which updates on
I CHANNEL –70 2ND 5TH 6TH 4TH 7TH
the rising edge of the input clock. A logic multiplexer, con-
–80 3RD 9TH 8TH
trolled through the SELECT pin, determines which channel is
–90
passed to the digital output pins. The output drivers have their
–100
own supply (DVDD), allowing the part to be interfaced to a
–110
variety of logic families. The outputs can be placed in a high
–120 0.0E+0 1.0E+6 2.0E+6 3.0E+6 4.0E+6 5.0E+6 6.0E+6 7.0E+6 8.0E+6 9.0E+6 10.0E+6
impedance state using the CHIP SELECT pin.
10
The AD9201 has great flexibility in its supply voltage. The
FUND 0
analog and digital supplies may be operated from 2.7 V to 5.5 V,
–10
independently of one another.
–20 –30 ANALOG INPUT –40
Figure 16 shows an equivalent circuit structure for the analog
–50
input of one of the A/D converters. PMOS source-followers
–60
buffer the analog input pins from the charge kickback problems
Q CHANNEL –70 5TH 4TH 6TH 7TH 8TH 9TH
normally associated with switched capacitor ADC input struc-
–80 3RD 2ND
tures. This produces a very high input impedance on the part,
–90
allowing it to be effectively driven from high impedance sources.
–100
This means that the AD9201 could even be driven directly by a
–110
passive antialias filter.
–120 0.0E+0 1.0E+6 2.0E+6 3.0E+6 4.0E+6 5.0E+6 6.0E+6 7.0E+6 8.0E+6 9.0E+6 10.0E+6
Figure 15. Simultaneous Operation of I and Q Channels (Differential Input)
IINA BUFFER OUTPUT WORD ADC THEORY OF OPERATION CORE SHA
The AD9201 integrates two A/D converters, two analog input
+FS –FS LIMIT LIMIT
buffers, an internal reference and reference buffer, and an out- put multiplexer. For clarity, this data sheet refers to the two
IINB BUFFER +FS LIMIT = –FS LIMIT =
converters as “I” and “Q.” The two A/D converters simulta-
VREF +VREF/2 VREF –VREF/2
neously sample their respective inputs on the rising edge of the input clock. The two converters distribute the conversion opera-
VREF
tion over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes the result from Figure 16. Equivalent Circuit for AD9201 Analog Inputs stage to stage. As a consequence of the distributed conversion, The source followers inside the buffers also provide a level-shift each converter requires a small fraction of the 1023 comparators function of approximately 1 V, allowing the AD9201 to accept used in a traditional flash-type 10-bit ADC. A sample-and-hold inputs at or below ground. One consequence of this structure is function within each of the stages permits the first stage to oper- that distortion will result if the analog input approaches the ate on a new input sample while the following stages continue to positive supply. For optimum high frequency distortion perfor- process previous samples. This results in a “pipeline processing” mance, the analog input signal should be centered according latency of three clock periods between when an input sample is to Figure 29. taken and when the corresponding ADC output is updated into the output registers. The capacitance load of the analog input Pin is 4 pF to the analog supplies (AVSS, AVDD). The AD9201 integrates input buffer amplifiers to drive the analog inputs of the converters. In most applications, these Full-scale setpoints may be calculated according to the following input amplifiers eliminate the need for external op amps for the algorithm (VREF may be internally or externally generated): input signals. The input structure is fully differential, but the –FS = (VREF – VREF/2) SHA common-mode response has been designed to allow the +FS = (VREF + VREF/2) converter to readily accommodate either single-ended or differ- VSPAN = VREF ential input signals. This differential structure makes the part capable of accommodating a wide range of input signals. –8– REV. D