Datasheet AD6640 (Analog Devices) - 4

AD6640 SWITCHING SPECIFICATIONS1 (AVCC = +5 V, DVCC = +3.3 V; ENCODE and ENCODE = 65 MSPS; TMIN = –40
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C, TMAX = +85
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C, unless otherwise noted.) Test AD6640AST Parameter (Conditions) Temp Level Min Typ Max Unit
Maximum Conversion Rate Full VI 65 MSPS Minimum Conversion Rate2 Full IV 6.5 MSPS Aperture Delay (tA) +25°C V 400 ps Aperture Uncertainty (Jitter) +25°C V 0.3 ps rms ENCODE Pulsewidth High3 +25°C IV 6.5 ns ENCODE Pulsewidth Low +25°C IV 6.5 ns Output Delay (tOD) DVCC + 3.3 V/5.0 V4 Full IV 8.5 10.5 12.5 ns NOTES 1All switching specifications tested by driving ENCODE and ENCODE differentially. 2A plot of Performance versus ENCODE is shown in TPC 10. 3A plot of Performance versus Duty Cycle (ENCODE = 65 MSPS) is shown in TPC 11. 4Outputs driving one LCX gate. Delay is measured from differential crossing of ENCODE and ENCODE to the time when all output data bits are within valid logic levels. Specifications subject to change without notice.
(AV AC SPECIFICATIONS1 CC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 65 MSPS; TMIN = –40
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C, TMAX = +85
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C, unless otherwise noted.) Test AD6640AST Parameter (Conditions) Temp Level Min Typ Max Unit
SNR Analog Input 2.2 MHz +25°C V 68 dB @ –1 dBFS 15.5 MHz +25°C I 64 67.7 dB 31.0 MHz +25°C V 67.5 dB 69.0 MHz +25°C V 66 dB SINAD Analog Input 2.2 MHz +25°C V 68 dB @ –1 dBFS 15.5 MHz +25°C I 63.5 67.2 dB 31.0 MHz +25°C V 67.0 dB 69.0 MHz +25°C V 65.5 dB Worst Harmonic2 (2nd or 3rd) Analog Input 2.2 MHz +25°C V 80 dBc @ –1 dBFS 15.5 MHz +25°C I 74 80 dBc 31.0 MHz +25°C V 79.5 dBc 69.0 MHz +25°C V 78.5 dBc Worst Harmonic2 (4th or Higher) Analog Input 2.2 MHz +25°C V 85 dBc @ –1 dBFS 15.5 MHz +25°C I 74 85 dBc 31.0 MHz +25°C V 85 dBc 69.0 MHz +25°C V 84 dBc Multitone SFDR (with Dither)3 Eight Tones @ –20 dBFS Full V 90 dBFS Two-Tone IMD Rejection4 F1, F2 @ –7 dBFS Full V 80 dBc Analog Input Bandwidth5 +25°C V 300 MHz NOTES 1All ac specifications tested by driving ENCODE and ENCODE differentially. 2For a single test tone at –1 dBFS, the worst-case spectral performance is typically limited by the direct or aliased second or third harmonic. If a system is designed such that the second and third harmonics fall out-of-band, overall performance in the band of interest is typically improved by 5 dB. Worst harmonic (fourth or higher) includes fourth and higher order harmonics and all other spurious components. Reference TPC 6 for more detail. 3See Overcoming Static Nonlinearities with Dither section for details on improving SFDR performance. To measure SFDR, eight tones from 14 MHz to 18 MHz (0.5 MHz spacing) are swept from –20 dBFS to –90 dBFS. An open channel at 16 MHz is used to monitor SFDR. 4F1 = 14.9 MHz, F2 = 16 MHz. 5Specification is small signal bandwidth. Plots of Performance versus Analog Input Frequency are shown in TPCs 4, 5, and 6. Sampling wide bandwidths (5 MHz–15 MHz) should be limited to 70 MHz center frequency. Specifications subject to change without notice. REV. A –3– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal) Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Power Supply Rejection Ratio Signal-to-Noise-and-Distortion (SINAD) Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR Worst Harmonic Equivalent Circuits Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD6640 Encoding the AD6640 Driving the Analog Input Power Supplies Output Loading Layout Information Evaluation Boards DIGITAL WIDEBAND RECEIVERS Introduction System Description System Requirements Noise Floor and SNR Processing Gain Overcoming Static Nonlinearities with Dither Receiver Example IF Sampling Using the AD6640 as a Mix-Down Stage RECEIVE CHAIN FOR A PHASED-ARRAY CELLULAR BASE STATION OUTLINE DIMENSIONS Revision History