Datasheet AD7731 (Analog Devices) - 8

AD7731 INPUT CHOPPING SINC3 FILTER SKIP MODE 22-TAP FIR FILTER THE ANALOG INPUT TO THE PART THE FIRST STAGE OF THE DIGITAL IN SKIP MODE, THERE IS NO WITH SKIP DISABLED, THE NORMAL CAN BE CHOPPED. IN CHOPPING MODE, FILTERING ON THE PART IS THE SECOND STAGE OF FILTERING ON OPERATING MODE OF THE SECOND STAGE THE INPUT IS CHOPPEDAND THE OUTPUT OF SINC3 FILTER. THE OUTPUT UPDATE THE PART. THE SINC3 FILTER IS OF THE DIGITAL FILTERING ON THE PART IS THE FIRST STAGE FILTER IS CHOPPED RATE AND BANDWIDTH OF THIS THE ONLY FILTERING PERFORMED A FIXED 22-TAP FIR FILTER. IN SKIP MODE, THIS FIR FILTER IS BYPASSED. WHEN REMOVING ERRORS IN THAT PATH. FILTER CAN BE PROGRAMMED. IN ON THE PART. THIS IS THE FASTSTEP™ MODE IS ENABLED AND A THE DEFAULT CONDITION IS SKIP MODE, THE SINC3 FILTER IS SECOND STAGE FILTER STEP INPUT IS DETECTED, THE SECOND CHOPPING DISABLED THE ONLY FILTERING PERFORMED SEE PAGE 25 STAGE FILTERING IS PERFORMED BY THE ON THE P3T. SEE PAGE 25 FAST STEP FILTER UNTIL THE OUTPUT OF THIS FILTER HAS FULLY SETTLED SEE PAGE 25 SEE PAGE 26 22-TAP FIR FILTER PGA & SKIP ANALOG SINC3 OUTPUT CHOP DIGITAL BUFFER SIGMA-DELTA CHOP INPUT FILTER SCALING OUTPUT MODULATOR FASTSTEP™ FILTER BUFFER PGA & SIGMA-DELTA OUTPUT CHOPPING FASTSTEP™ FILTER OUTPUT SCALING YY MODULATOR THE INPUT SIGNAL IS BUFFERED THE OUTPUT OF THE FIRST STAGE THE OUTPUT WORD FROM THE ON-CHIP BEFORE BEING APPLIED OF FILTERING ON THE PART CAN WHEN FASTSTEP™ MODE IS DIGITAL FILTER IS SCALED BY THE THE PROGRAMMABLE GAIN TO THE SAMPLING CAPACITOR OF BE CHOPPED. THE DEFAULT ENABLED AND A STEP CHANGE ON CALIBRATION COEFFICIENTS CAPABILITY OF THE PART IS THE SIGMA DELTA MODULATOR. CONDITION IS CHOPPING THE INPUT HAS BEEN DETECTED, BEFORE BEING PROVIDED AS THE INCORPORATED AROUND THE THIS ISOLATES THE SAMPLING THE SECOND STAGE FILTERING IS SIGMA DELTA MODULATOR.THE DISABLED CONVERSION RESULT CAPACITOR CHARGING CURRENTS PERFORMED BY THE FASTSTEP™ MODULATOR PROVIDES A HIGH- SEE PAGE 29 SEE PAGE 25 FILTER UNTIL THE FIR FILTER HAS FROM THE ANALOG INPUT PINS FREQUENCY 1-BIT DATA STREAM FULLY SETTLED. TO THE DIGITAL FILTER. SEE PAGE 23 SEE PAGE 28 SEE PAGE 24
Figure 3. Signal Processing Chain
PIN CONFIGURATION SCLK 1 24 DGND MCLK IN 2 23 DVDD MCLK OUT 3 22 DIN POL 4 21 DOUT SYNC 5 20 RDY AD7731 RESET 6 19 CS TOP VIEW NC 7 18 STANDBY (Not to Scale) AGND 8 17 AIN6 AV 9 16 AIN5 DD AIN1 10 15 REF IN(–) AIN2 11 14 REF IN(+) AIN3/D1 12 13 AIN4/D0 NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin Pin No. Mnemonic Function
1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer serial data to or from the AD7731. This serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being trans- mitted to or from the AD7731 in smaller batches of data. 2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part is specified with a clock input frequency of 4.9152 MHz. REV. 0 REV. A –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM AD7731-SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Ordering Guide ESD Caution PIN CONFIGURATION Pin Function Descriptions TERMINOLOGY OUTPUT NOISE AND RESOLUTION SPECIFICATION Output Noise (CHP = 0, SKIP= 1) Output Noise (CHP = 1, SKIP = 0) ON-CHIP REGISTERS Communications Register (RS2-RS0 = 0, 0, 0) Status Register (RS2-RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex Data Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex Mode Register (RS2-RS0 = 0, 1, 0); Power-On/Reset Status: 0174 Hex Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 2002 Hex Offset Calibration Register (RS2-RS0 = 1, 0, 1) Gain Calibration Register (RS2-RS0 = 1, 1, 0) Test Register (RS2-RS0 = 1, 1, 1); Power On/Reset Status: 000000 Hex READING FROM AND WRITING TO THE ON-CHIP REGISTERS CALIBRATION OPERATION SUMMARY CIRCUIT DESCRIPTION ANALOG INPUT Analog Input Channels Buffered Inputs Analog Input Ranges Programmable Gain Amplifier Bipolar/Unipolar Inputs Burnout Currents REFERENCE INPUT Reference Detect SIGMA-DELTA MODULATOR DIGITAL FILTERING Filter Architecture First State Filter/SKIP Mode Enabled (SKIP =1) Nonchop Mode (SKIP =1, CHP = 0) Chop Mode (SKIP = 1, CHP =1) Second Stage Filter Normal FIR Operation (SKIP = 0) Chop Mode (SKIP = 0, CHP =1) Nonchop Mode (SKIP = 1, CHP = 0) FASTStep Mode (SKIP = 0, FAST = 1) CALIBRATION Internal Zero-Scale Calibration Internal Full-Scale Calibration System Zero-Scale Calibration System Full-Scale Calibration Span and Offset Limits Power-Up and Calibration Drift Considerations USING THE AD7731 Clocking and Oscillator Circuit System Synchronization Single-Shot Conversions Reset Input Standby Mode Digital Outputs POWER SUPPLIES Grounding and Layout Evaluting the AD7731 Performance SERIAL INTERFACE Write Operation Read Operation CONFIGURING THE AD7731 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7731 to 68HC11 Interface AD7731 to 8051 Interface AD7731 to ADSP-2103/ADSP-2105 Interface APPLICATIONS Data Acquisition Programmable Logic Controllers Pressure Measurement Temperature Measurement Bipolar Input Signals PAGE INDEX TABLE INDEX OUTLINE DIMENSIONS