Datasheet AD9280 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 8-Bit, Complete, 32 MSPS A/D Converter |
| 页数 / 页 | 25 / 4 — AD9280. Parameter. Symbol. Min. Typ. Max. Units. Condition. 10k. REFTS. … |
| 修订版 | E |
| 文件格式/大小 | PDF / 443 Kb |
| 文件语言 | 英语 |
AD9280. Parameter. Symbol. Min. Typ. Max. Units. Condition. 10k. REFTS. REFTF. 4.2k. REFBS. REFBF. 0.4. VDD. MODE
该数据表的模型线
文件文字版本
AD9280 Parameter Symbol Min Typ Max Units Condition
DIGITAL INPUTS High Input Voltage VIH 2.4 V Low Input Voltage VIL 0.3 V DIGITAL OUTPUTS High-Z Leakage IOZ –10 +10 µA Output = GND to VDD Data Valid Delay tOD 25 ns CL = 20 pF Data Enable Delay tDEN 25 ns Data High-Z Delay tDHZ 13 ns LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) VOH +2.95 V High Level Output Voltage (IOH = 0.5 mA) VOH +2.80 V Low Level Output Voltage (IOL = 1.6 mA) VOL +0.4 V Low Level Output Voltage (IOL = 50 µA) VOL +0.05 V LOGIC OUTPUT (with DRVDD = 5 V) High Level Output Voltage (IOH = 50 µA) VOH +4.5 V High Level Output Voltage (IOH = 0.5 mA) VOH +2.4 V Low Level Output Voltage (IOL = 1.6 mA) VOL +0.4 V Low Level Output Voltage (IOL = 50 µA) VOL +0.1 V CLOCKING Clock Pulsewidth High tCH 14.7 ns Clock Pulsewidth Low tCL 14.7 ns Pipeline Latency 3 Cycles CLAMP Clamp Error Voltage E ± OC 60 ±80 mV CLAMPIN = +0.5 V to +2.0 V, RIN = 10 Ω Clamp Pulsewidth tCPW 2 µs CIN = 1 µF (Period = 63.5 µs) NOTES 1See Figures 1a and 1b. Specifications subject to change without notice.
10k
V
REFTS REFTS AD9280 AD9280 REFTF 4.2k
V
10k
V
REFBS REFBF 0.4
3
VDD REFBS MODE AV MODE DD
a. b. Figure 1. Equivalent Input Load REV. E –3– Document Outline FEATURES PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM AD9280-SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITIONS OF SPECIFICATIONS TYPICAL CHARACTERIZATION CURVES APPLYING THE AD9280 Theory of Operation Operational Modes Summary of Modes Voltage Reference Reference Buffer Analog Input Special Input and Reference Overview REFERENCE OPERATION Internal Reference Operation External Reference Operation STANDBY OPERATION CLAMP OPERATION Clamp Circuit Example DRIVING THE ANALOG INPUT DIFFERENTIAL INPUT OPERATION AD876-8 MODE OF OPERATION CLOCK INPUT DIGITAL INPUTS AND OUTPUTS APPLICATIONS Direct IF Down Conversion Using the AD9280 Grounding and Layout Rules Digital Outputs Three-State Outputs OUTLINE DIMENSIONS Ordering Guide REVISION HISTORY
DIGITAL INPUTS High Input Voltage VIH 2.4 V Low Input Voltage VIL 0.3 V DIGITAL OUTPUTS High-Z Leakage IOZ –10 +10 µA Output = GND to VDD Data Valid Delay tOD 25 ns CL = 20 pF Data Enable Delay tDEN 25 ns Data High-Z Delay tDHZ 13 ns LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) VOH +2.95 V High Level Output Voltage (IOH = 0.5 mA) VOH +2.80 V Low Level Output Voltage (IOL = 1.6 mA) VOL +0.4 V Low Level Output Voltage (IOL = 50 µA) VOL +0.05 V LOGIC OUTPUT (with DRVDD = 5 V) High Level Output Voltage (IOH = 50 µA) VOH +4.5 V High Level Output Voltage (IOH = 0.5 mA) VOH +2.4 V Low Level Output Voltage (IOL = 1.6 mA) VOL +0.4 V Low Level Output Voltage (IOL = 50 µA) VOL +0.1 V CLOCKING Clock Pulsewidth High tCH 14.7 ns Clock Pulsewidth Low tCL 14.7 ns Pipeline Latency 3 Cycles CLAMP Clamp Error Voltage E ± OC 60 ±80 mV CLAMPIN = +0.5 V to +2.0 V, RIN = 10 Ω Clamp Pulsewidth tCPW 2 µs CIN = 1 µF (Period = 63.5 µs) NOTES 1See Figures 1a and 1b. Specifications subject to change without notice.
10k
V
REFTS REFTS AD9280 AD9280 REFTF 4.2k
V
10k
V
REFBS REFBF 0.4
3
VDD REFBS MODE AV MODE DD
a. b. Figure 1. Equivalent Input Load REV. E –3– Document Outline FEATURES PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM AD9280-SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITIONS OF SPECIFICATIONS TYPICAL CHARACTERIZATION CURVES APPLYING THE AD9280 Theory of Operation Operational Modes Summary of Modes Voltage Reference Reference Buffer Analog Input Special Input and Reference Overview REFERENCE OPERATION Internal Reference Operation External Reference Operation STANDBY OPERATION CLAMP OPERATION Clamp Circuit Example DRIVING THE ANALOG INPUT DIFFERENTIAL INPUT OPERATION AD876-8 MODE OF OPERATION CLOCK INPUT DIGITAL INPUTS AND OUTPUTS APPLICATIONS Direct IF Down Conversion Using the AD9280 Grounding and Layout Rules Digital Outputs Three-State Outputs OUTLINE DIMENSIONS Ordering Guide REVISION HISTORY