Datasheet AD9280 (Analog Devices) - 9

AD9280 0 APPLYING THE AD9280 –3 THEORY OF OPERATION
The AD9280 implements a pipelined multistage architecture to
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achieve high sample rate with low power. The AD9280 distrib- utes the conversion over several smaller A/D subblocks, refining
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the conversion with progressively higher accuracy as it passes
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the results from stage to stage. As a consequence of the distrib- uted conversion, the AD9280 requires a small fraction of the
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256 comparators used in a traditional flash type A/D. A sample- and-hold function within each of the stages permits the first
SIGNAL AMPLITUDE – dB –18
stage to operate on a new input sample while the second, third
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and fourth stages operate on the three preceding samples.
–24 1.0E+6 1.0E+7 1.0E+8 1.0E+9 OPERATIONAL MODES FREQUENCY – Hz
The AD9280 is designed to allow optimal performance in a Figure 13. Full Power Bandwidth wide variety of imaging, communications and instrumentation applications, including pin compatibility with the AD876-8 A/D.
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To realize this flexibility, internal switches on the AD9280 are
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used to reconfigure the circuit into different modes. These modes are selected by appropriate pin strapping. There are three parts
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of the circuit affected by this modality: the voltage reference, the
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reference buffer, and the analog input. The nature of the appli-
REFBS = 0.5V 10 REFTS = 2.5V
cation will determine which mode is appropriate: the descrip-
A CLOCK = 32MHz
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tions in the following sections, as well as Table I should assist in
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selecting the desired mode.
–10 –20 –30 –40 –500 0.5 1.0 1.5 2.0 2.5 3.0 INPUT VOLTAGE – V
Figure 14. Input Bias Current vs. Input Voltage
Table I. Mode Selection Input Input MODE REFSENSE Modes Connect Span Pin Pin REF REFTS REFBS Figure
TOP/BOTTOM AIN 1 V AVDD Short REFSENSE, REFTS and VREF Together AGND 18 AIN 2 V AVDD AGND Short REFTS and VREF Together AGND 19 CENTER SPAN AIN 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 20 AIN 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2 Differential AIN Is Input 1 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 29 REFTS and REFBS Are Shorted Together for Input 2 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2 External Ref AIN 2 V max AVDD AVDD No Connect Span = REFTS 21, 22 – REFBS (2 V max) AGND Short to Short to 23 VREFTF VREFBF AD876-8 AIN 2 V Float or AVDD No Connect Short to Short to 30 AVSS VREFTF VREFBF –8– REV. E Document Outline FEATURES PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM AD9280-SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITIONS OF SPECIFICATIONS TYPICAL CHARACTERIZATION CURVES APPLYING THE AD9280 Theory of Operation Operational Modes Summary of Modes Voltage Reference Reference Buffer Analog Input Special Input and Reference Overview REFERENCE OPERATION Internal Reference Operation External Reference Operation STANDBY OPERATION CLAMP OPERATION Clamp Circuit Example DRIVING THE ANALOG INPUT DIFFERENTIAL INPUT OPERATION AD876-8 MODE OF OPERATION CLOCK INPUT DIGITAL INPUTS AND OUTPUTS APPLICATIONS Direct IF Down Conversion Using the AD9280 Grounding and Layout Rules Digital Outputs Three-State Outputs OUTLINE DIMENSIONS Ordering Guide REVISION HISTORY