Datasheet AD7819 (Analog Devices) - 8

AD7819
During the acquisition phase the sampling capacitor must be When operating in Mode 2, the ADC is powered down at the charged to within a 1/2 LSB of its final value. The time it takes end of each conversion and powered up again before the next to charge the sampling capacitor (TCHARGE) is given by the fol- conversion is initiated. (See Figure 8.) lowing formula:
MODE 1
TCHARGE = 6.2 × (R2 + 125 Ω) × 3.5 pF
V
For small values of source impedance, the settling time associ-
DD
ated with the sampling circuit (100 ns) is, in effect, the acquisition
EXT CONVST
time of the ADC. For example, with a source impedance (R2)
t POWER-UP
of 10 Ω, the charge time for the sampling capacitor is approxi-
1.5 s
mately 3 ns. The charge time becomes significant for source
INT CONVST
impedances of 2 kΩ and greater.
AC Acquisition Time MODE 2
In ac applications it is recommended to always buffer analog input signals. The source impedance of the drive circuitry must
VDD
be kept as low as possible to minimize the acquisition time of the ADC. Large values of source impedance will cause the THD to
EXT CONVST t
degrade at high throughput rates.
tPOWER-UP P OWER-UP 1.5 s 1.5 s ADC TRANSFER FUNCTION INT CONVST
The output coding of the AD7819 is straight binary. The designed code transitions occur at successive integer LSB values (i.e., Figure 8. Power-Up Times 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/256. The ideal transfer characteristic for the AD7819 is shown in Figure 7 below.
POWER VS. THROUGHPUT RATE
By operating the AD7819 in Mode 2, the average power con- sumption of the AD7819 decreases at lower throughput rates.
111...111
Figure 9 shows how the Automatic Power-Down is implemented
111...110 • •
using the external CONVST signal to achieve the optimum
• 111...000
power performance for the AD7819. The AD7819 is operated
• 1LSB = V • REF/256
in Mode 2 and the duration of the external CONVST pulse is
011...111 ADC CODE •
set to be equal to or less than the power-up time of the device.
• • 000...010
As the throughput rate is reduced, the device remains in its power-
000...001
down state longer and the average power consumption over time
000...000
drops accordingly.
0V 1LSB +VREF –1LSB ANALOG INPUT
Figure 7. Transfer Characteristic
EXT CONVST t POWER-UP TIMES P OWER-UP 1.5 s tCONVERT
The AD7819 has a 1.5 µs power-up time. When V
POWER-DOWN 4.5 s
DD is first con- nected, the AD7819 is in a low current mode of operation. In
INT CONVST
order to carry out a conversion the AD7819 must first be pow-
tCYCLE
ered up. The ADC is powered up by a rising edge on an internally
100 s @ 10kSPS
generated CONVST signal, which occurs as a result of a rising edge on the external CONVST pin. The rising edge of the external Figure 9. Automatic Power-Down CONVST signal initiates a 1.5 µs pulse on the internal CONVST If, for example, the AD7819 is operated in a continuous sam- signal. This pulse is present to ensure the part has enough time pling mode with a throughput rate of 10 kSPS, the power to power-up before a conversion is initiated, as a conversion is consumption is calculated as follows. The power dissipation initiated on the falling edge of gated CONVST. See Timing and during normal operation is 10.5 mW, VDD = 3 V. If the power- Control section. Care must be taken to ensure that the CONVST up time is 1.5 µs and the conversion time is 4.5 µs, the AD7819 pin of the AD7819 is logic low when VDD is first applied. can be said to dissipate 10.5 mW for 6 µs (worst case) during each conversion cycle. If the throughput rate is 10 kSPS, the cycle time is then 100 µs and the average power dissipated dur- ing each cycle is (6/100) × (10.5 mW) = 630 µW. REV. B –7–