Datasheet AD7813 (Analog Devices) - 10

AD7813 t1 t2 EXT CONVST t3 t POWER-UP INT CONVST BUSY CS/RD DB7–DB0 8 MSBs 2 LSBs
Figure 13. Mode 1 Operation
EXT CONVST t POWER-UP t1 INT CONVST t3 BUSY CS/RD DB7–DB0 8 MSBs
Figure 14. Mode 2 Operation
PARALLEL INTERFACE
Further read operations will access the 8 MSBs and 2 LSBs of The parallel interface of the AD7813 is eight bits wide. The the 10-bit ADC conversion result again. The parallel interface output data buffers are activated when both CS and RD are of the AD7813 is reset when BUSY goes logic high. This feature logic low. At this point the contents of the data register are allows the AD7813 to be used as an 8-bit converter if the user placed on the 8-bit data bus. Figure 15 shows the timing dia- only wishes to access the 8 MSBs of the conversion. Care must gram for the parallel port. As previously explained, two succes- be taken to ensure that a read operation does not occur while sive read operations must take place in order to access the 10-bit BUSY is high. Data read from the AD7813 while BUSY is high conversion result. The first read places the 8 MSBs on the data will be invalid. For optimum performance the read operation bus and the second read places the 2 LSBs on the data bus. The should end at least 100 ns (t10) prior to the falling edge of the 2 LSBs appear on DB7 and DB6, with DB5–DB0 set to logic zero. next CONVST.
CONVST t2 t t 9 3 BUSY t1 t8 CS t4 t5 RD t7 t6 DB7–DB0 8 MSBs 2 MSBs
Figure 15. Parallel Port Timing REV. C –9–