Datasheet AD9241 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Complete 14-Bit, 1.25 MSPS Monolithic A/D Converter |
| 页数 / 页 | 25 / 10 — AD9241. –40. –45. –50. –55. –60. –65. THD – dB. –70. –75. VCM = 1V. … |
| 文件格式/大小 | PDF / 538 Kb |
| 文件语言 | 英语 |
AD9241. –40. –45. –50. –55. –60. –65. THD – dB. –70. –75. VCM = 1V. AMPLITUDE – dB. –80. VCM = 2.5V. –10. –85. 0.01. 0.1. 1.0. 10.0. FREQUENCY – MHz. –12. 100. 16000
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AD9241
The input SHA of the AD9241 is optimized to meet the perfor- 1 V and 2.5 V. Note the difference in the amount of degrada- mance requirements for some of the most demanding commu- tion in THD performance as the input frequency increases. nication, imaging and data acquisition applications, while Similarly, note how the THD performance at lower frequencies maintaining low power dissipation. Figure 22 is a graph of the becomes less sensitive to the common-mode voltage. As the full-power bandwidth of the AD9241, typically 40 MHz. Note input frequency approaches dc, the distortion will be domi- that the small signal bandwidth is the same as the full-power nated by static nonlinearities such as INL and DNL. It is bandwidth. The settling time response to a full-scale stepped important to note that these dc static nonlinearities are inde- input is shown in Figure 23 and is typically less than 80 ns to pendent of any RON modulation. 0.0025%. The low input referred noise of 0.36 LSB’s rms is displayed via a grounded histogram and is shown in Figure 13.
–40 –45 2 –50 0 –55 –2 –60 –65 –4 THD – dB –70 –6 –75 VCM = 1V AMPLITUDE – dB –8 –80 VCM = 2.5V –10 –85 0.01 0.1 1.0 10.0 FREQUENCY – MHz –12 0.01 0.1 1.0 10.0 100
Figure 24. THD vs. Frequency for V
FREQUENCY – MHz
CM = 2.5 V and 1.0 V (AIN = –0.5 dB, Input Span = 2.0 V p-p) Figure 22. Full-Power Bandwidth Due to the high degree of symmetry within the SHA topology, a significant improvement in distortion performance for differen-
16000
tial input signals with frequencies up to and beyond Nyquist can be realized. This inherent symmetry provides excellent cancella- tion of both common-mode distortion and noise. In addition,
12000
the required input signal voltage span is reduced by a factor of two, which further reduces the degree of RON modulation and its effects on distortion.
8000 CODE
The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 5 V input span) and matched
4000
input impedance for VINA and VINB. Note that only a slight degradation in dc linearity performance exists between the 2 V and 5 V input span as specified in AD9241 DC SPECIFICATIONS.
0 0 10 20 30 40 50 60 70 80
Referring to Figure 21, the differential SHA is implemented
SETTLING TIME – ns
using a switched-capacitor topology. Hence, its input imped- ance and its subsequent effects on the input drive source should Figure 23. Settling Time be understood to maximize the converter’s performance. The The SHA’s optimum distortion performance for a differential or combination of the pin capacitance, CPIN, parasitic capacitance single-ended input is achieved under the following two condi- CPAR, and the sampling capacitance, CS, is typically less than tions: (1) the common-mode voltage is centered around mid- 16 pF. When the SHA goes into track mode, the input source supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input must charge or discharge the voltage stored on CS to the new signal voltage span of the SHA is set at its lowest (i.e., 2 V input input voltage. This action of charging and discharging CS, which span). This is due to the sampling switches, Q is approximately 4 pF, averaged over a period of time and for a S1, being CMOS switches whose R given sampling frequency, F ON resistance is very low but has some signal S, makes the input impedance ap- dependency causing frequency-dependent ac distortion while pear to have a benign resistive component (i.e., 83 kΩ at FS = the SHA is in the track mode. The R 1.25 MSPS). However, if this action is analyzed within a sam- ON resistance of a CMOS switch is typically lowest at its midsupply, but increases sym- pling period (i.e., T = <1/FS), the input impedance is dynamic metrically as the input signal approaches either AVDD or due to the instantaneous requirement of charging and discharg- AVSS. A lower input signal voltage span centered at midsupply ing CS. A series resistor inserted between the input drive source reduces the degree of R and the SHA input, as shown in Figure 25, provides effective ON modulation. isolation. Figure 24 compares the AD9241’s THD vs. frequency perfor- mance for a 2 V input span with a common-mode voltage of REV. 0 –9–
The input SHA of the AD9241 is optimized to meet the perfor- 1 V and 2.5 V. Note the difference in the amount of degrada- mance requirements for some of the most demanding commu- tion in THD performance as the input frequency increases. nication, imaging and data acquisition applications, while Similarly, note how the THD performance at lower frequencies maintaining low power dissipation. Figure 22 is a graph of the becomes less sensitive to the common-mode voltage. As the full-power bandwidth of the AD9241, typically 40 MHz. Note input frequency approaches dc, the distortion will be domi- that the small signal bandwidth is the same as the full-power nated by static nonlinearities such as INL and DNL. It is bandwidth. The settling time response to a full-scale stepped important to note that these dc static nonlinearities are inde- input is shown in Figure 23 and is typically less than 80 ns to pendent of any RON modulation. 0.0025%. The low input referred noise of 0.36 LSB’s rms is displayed via a grounded histogram and is shown in Figure 13.
–40 –45 2 –50 0 –55 –2 –60 –65 –4 THD – dB –70 –6 –75 VCM = 1V AMPLITUDE – dB –8 –80 VCM = 2.5V –10 –85 0.01 0.1 1.0 10.0 FREQUENCY – MHz –12 0.01 0.1 1.0 10.0 100
Figure 24. THD vs. Frequency for V
FREQUENCY – MHz
CM = 2.5 V and 1.0 V (AIN = –0.5 dB, Input Span = 2.0 V p-p) Figure 22. Full-Power Bandwidth Due to the high degree of symmetry within the SHA topology, a significant improvement in distortion performance for differen-
16000
tial input signals with frequencies up to and beyond Nyquist can be realized. This inherent symmetry provides excellent cancella- tion of both common-mode distortion and noise. In addition,
12000
the required input signal voltage span is reduced by a factor of two, which further reduces the degree of RON modulation and its effects on distortion.
8000 CODE
The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 5 V input span) and matched
4000
input impedance for VINA and VINB. Note that only a slight degradation in dc linearity performance exists between the 2 V and 5 V input span as specified in AD9241 DC SPECIFICATIONS.
0 0 10 20 30 40 50 60 70 80
Referring to Figure 21, the differential SHA is implemented
SETTLING TIME – ns
using a switched-capacitor topology. Hence, its input imped- ance and its subsequent effects on the input drive source should Figure 23. Settling Time be understood to maximize the converter’s performance. The The SHA’s optimum distortion performance for a differential or combination of the pin capacitance, CPIN, parasitic capacitance single-ended input is achieved under the following two condi- CPAR, and the sampling capacitance, CS, is typically less than tions: (1) the common-mode voltage is centered around mid- 16 pF. When the SHA goes into track mode, the input source supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input must charge or discharge the voltage stored on CS to the new signal voltage span of the SHA is set at its lowest (i.e., 2 V input input voltage. This action of charging and discharging CS, which span). This is due to the sampling switches, Q is approximately 4 pF, averaged over a period of time and for a S1, being CMOS switches whose R given sampling frequency, F ON resistance is very low but has some signal S, makes the input impedance ap- dependency causing frequency-dependent ac distortion while pear to have a benign resistive component (i.e., 83 kΩ at FS = the SHA is in the track mode. The R 1.25 MSPS). However, if this action is analyzed within a sam- ON resistance of a CMOS switch is typically lowest at its midsupply, but increases sym- pling period (i.e., T = <1/FS), the input impedance is dynamic metrically as the input signal approaches either AVDD or due to the instantaneous requirement of charging and discharg- AVSS. A lower input signal voltage span centered at midsupply ing CS. A series resistor inserted between the input drive source reduces the degree of R and the SHA input, as shown in Figure 25, provides effective ON modulation. isolation. Figure 24 compares the AD9241’s THD vs. frequency perfor- mance for a 2 V input span with a common-mode voltage of REV. 0 –9–