Datasheet AD9240 (Analog Devices) - 10

AD9240
The addition of a differential input structure gives the user an The input SHA of the AD9240 is optimized to meet the perfor- additional level of flexibility that is not possible with traditional mance requirements for some of the most demanding commu- flash converters. The input stage allows the user to easily con- nication, imaging, and data acquisition applications while figure the inputs for either single-ended operation or differential maintaining low power dissipation. Figure 25 is a graph of the operation. The A/D’s input structure allows the dc offset of the full-power bandwidth of the AD9240, typically 60 MHz. Note input signal to be varied independently of the input span of the that the small signal bandwidth is the same as the full-power converter. Specifically, the input to the A/D core is the differ- bandwidth. The settling time response to a full-scale stepped ence of the voltages applied at the VINA and VINB input pins. input is shown in Figure 26 and is typically less than 40 ns to 0.0025%. The low input referred noise of 0.36 LSB’s rms is Therefore, the equation, displayed via a grounded histogram and is shown in Figure 13. VCORE = VINA – VINB (1)
1
defines the output of the differential input stage and provides
0
the input to the A/D core.
–1
The voltage, VCORE, must satisfy the condition,
–2
–VREF ≤ VCORE ≤ VREF
–3
(2)
–4
where VREF is the voltage at the VREF pin.
–5
While an infinite combination of VINA and VINB inputs exist
–6 AMPLITUDE – dB
that satisfy Equation 2, there is an additional limitation placed
–7
on the inputs by the power supply voltages of the AD9240. The
–8
power supplies bound the valid operating range for VINA and
–9
VINB. The condition,
–10 1 10 100
AVSS – 0.3 V < VINA < AVDD + 0.3 V
FREQUENCY – MHz
(3) Figure 25. Full-Power Bandwidth AVSS – 0.3 V < VINB < AVDD + 0.3 V where AVSS is nominally 0 V and AVDD is nominally +5 V,
16000
defines this requirement. Thus, the range of valid inputs for VINA and VINB is any combination that satisfies both Equa- tions 2 and 3.
12000
For additional information showing the relationship between VINA, VINB, VREF and the digital output of the AD9240, see Table IV.
8000 CODE
Refer to Table I and Table II for a summary of the various analog input and reference configurations
. 4000 ANALOG INPUT OPERATION
Figure 24 shows the equivalent analog input of the AD9240 which consists of a differential sample-and-hold amplifier (SHA).
00 10 20 30 40 50 60 70 80
The differential input structure of the SHA is highly flexible,
SETTLING TIME – ns
allowing the devices to be easily configured for either a differen- Figure 26. Settling Time tial or single-ended input. The dc offset, or common-mode voltage, of the input(s) can be set to accommodate either single- The SHA’s optimum distortion performance for a differential or supply or dual supply systems. Note also that the analog inputs, single-ended input is achieved under the following two condi- VINA and VINB, are interchangeable with the exception that tions: (1) the common-mode voltage is centered around mid- reversing the inputs to the VINA and VINB pins results in a supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input polarity inversion. signal voltage span of the SHA is set at its lowest (i.e., 2 V input span). This is due to the sampling switches, QS1, being CMOS
C
switches whose R
H
ON resistance is very low but has some signal dependency which causes frequency dependent ac distortion
QS2
while the SHA is in the track mode. The RON resistance of a
C + PIN Q C C S1 S
CMOS switch is typically lowest at its midsupply but increases
PAR VINA
symmetrically as the input signal approaches either AVDD or
Q QH1 C S1 S
AVSS. A lower input signal voltage span centered at midsupply
VINB
reduces the degree of R
C –
ON modulation.
PIN QS2 CPAR CH
Figure 24. Simplified Input Circuit REV. B –9–