Datasheet AD7823 (Analog Devices) - 10

AD7823 Mode 2 Operation (Automatic Power-Down)
high for 1.5 µs after the rising edge before bringing it low to When used in this mode of operation, the part automatically initiate a conversion. If the CONVST signal goes low before powers down at the end of a conversion. This is achieved by 1.5 µs in time has elapsed, the power-up time is timed out inter- leaving the CONVST signal low until the end of the conversion. nally and a conversion is initiated. Hence the AD7823 is guaran- The timing diagram in Figure 15 shows how to operate the part teed to have always powered up before a conversion is initiated— in this mode. If the AD7823 is powered down, the rising edge of even if the CONVST pulsewidth is <1.5 µs. If the CONVST the CONVST pulse causes the part to power up. When the part width is >1.5 µs a conversion is initiated on the falling edge. has powered up (≈ 1.5 µs after the rising edge of CONVST), the CONVST signal is brought low, and a conversion is initiated
SERIAL INTERFACE
on this falling edge of the CONVST signal. The conversion The serial interface of the AD7823 consists of three wires, a takes 5 µs max and after this time, the conversion result is latched serial clock input SCLK, serial port enable CONVST and a into the serial shift register and the part powers down. Therefore, serial data output DOUT, see Figure 16 below. The serial inter- when the part is operated in Mode 2, the effective conversion face is designed to allow easy interfacing to most microcontrollers, time is equal to the power-up time (1.5 µs) and the SAR conver- e.g., PIC16C, PIC17C, QSPI and SPI, without the need for any sion time (5 µs), i.e., 6.5 µs. gluing logic. When interfacing to the 8051, the SCLK must be inverted. The “Microprocessor Interface” section explains how As in the case of Mode 1 operation, the rising edge of the CONVST to interface to some popular microcontrollers. pulse enables the serial port of the AD7823—see Serial Interface section. If a serial read is initiated soon after this Figure 16 shows the timing diagram for a serial read from the rising edge (Point “A”), i.e., before the end of the conversion, AD7823. The serial interface works with both a continuous and then the result of the previous conversion is shifted out on pin a noncontinuous serial clock. The rising edge of the CONVST D signal RESETS a counter, which counts the number of serial OUT. In order to read the result of the current conversion, the user must wait at least 5 µs max after the falling edge of CONVST clocks to ensure the correct number of bits are shifted out of the before initiating a serial read. The serial port of the AD7823 is serial shift registers. The SCLK is ignored once the correct still functional even though the AD7823 has been powered number of bits have been shifted out. In order for another serial down. Note: A serial read should not cross the reset rising edge transfer to take place, the counter must be reset by the falling of CONVST. edge of the eighth SCLK. Data is clocked out from the DOUT line on the first rising SCLK edge after the rising edge of the Because it is possible to do a serial read from the part while it is CONVST signal and on subsequent SCLK rising edges. The powered down, the AD7823 is powered up only to do the conver- D sion and is immediately powered down at the end of a conversion. OUT pin goes back into a high impedance state on the falling edge of the eighth SCLK. In multipackage applications, the This significantly improves the power consumption of the part CONVST signal can be used as a chip select signal. The serial at slower throughput rates—see Power vs. Throughput Rate interface will not shift data out until it receives a rising edge on section. the CONVST pin. Note: Although the AD7823 takes 1.5 µs to power up after the rising edge of CONVST, it is not necessary to leave CONVST
tPOWER-UP t1 1.5
␮
s CONVST SCLK A B CURRENT CONVERSION DOUT RESULT
Figure 15. Mode 2 Operation Timing
t3 SCLK 1 2 3 4 5 6 7 8 t t 4 5 CONVST t7 t t 8 6 DOUT DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 16. Serial Interface Timing REV. C –9–