Datasheet AD9243 (Analog Devices) - 9

AD9243 INTRODUCTION
Therefore, the equation, The AD9243 utilizes a four-stage pipeline architecture with a VCORE = VINA – VINB (1) wideband input sample-and-hold amplifier (SHA) implemented defines the output of the differential input stage and provides the on a cost-effective CMOS process. Each stage of the pipeline, input to the A/D core. excluding the last stage, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue The voltage, VCORE, must satisfy the condition, amplifier (MDAC). The residue amplifier amplifies the differ- –VREF ≤ VCORE ≤ VREF (2) ence between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used where VREF is the voltage at the VREF pin. in each of the stages to facilitate digital correction of flash er- While an infinite combination of VINA and VINB inputs exist rors. The last stage simply consists of a flash A/D. that satisfy Equation 2, there is an additional limitation placed The pipeline architecture allows a greater throughput rate at the on the inputs by the power supply voltages of the AD9243. The expense of pipeline delay or latency. This means that while the power supplies bound the valid operating range for VINA and converter is capable of capturing a new input sample every clock VINB. The condition, cycle, it actually takes three clock cycles for the conversion to be AVSS – 0.3 V < VINA < AVDD + 0.3 V (3) fully processed and appear at the output. This latency is not a AVSS – 0.3 V < VINB < AVDD + 0.3 V concern in most applications. The digital output, together with the out-of-range indicator (OTR), is latched into an output where AVSS is nominally 0 V and AVDD is nominally +5 V, buffer to drive the output pins. The output drivers can be con- defines this requirement. Thus, the range of valid inputs for figured to interface with +5 V or +3.3 V logic families. VINA and VINB is any combination that satisfies both Equa- tions 2 and 3. The AD9243 uses both edges of the clock in its internal timing circuitry (see Figure 1 and specification page for exact timing For additional information showing the relationship between requirements). The A/D samples the analog input on the rising VINA, VINB, VREF and the digital output of the AD9243, see edge of the clock input. During the clock low time (between the Table IV. falling edge and rising edge of the clock), the input SHA is in Refer to Table I and Table II for a summary of the various the sample mode; during the clock high time it is in the hold analog input and reference configurations
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mode. System disturbances just prior to the rising edge of the clock and/or excessive clock jitter may cause the input SHA to
ANALOG INPUT OPERATION
acquire the wrong value, and should be minimized. Figure 21 shows the equivalent analog input of the AD9243 which consists of a differential sample-and-hold amplifier (SHA).
ANALOG INPUT AND REFERENCE OVERVIEW
The differential input structure of the SHA is highly flexible, Figure 20, a simplified model of the AD9243, highlights the rela- allowing the devices to be easily configured for either a differen- tionship between the analog inputs, VINA, VINB, and the tial or single-ended input. The dc offset, or common-mode reference voltage, VREF. Like the voltage applied to the top voltage, of the input(s) can be set to accommodate either single- of the resistor ladder in a flash A/D converter, the value VREF supply or dual supply systems. Also, note that the analog inputs, defines the maximum input voltage to the A/D core. The minimum VINA and VINB, are interchangeable with the exception that input voltage to the A/D core is automatically defined to be –VREF. reversing the inputs to the VINA and VINB pins results in a polarity inversion.
AD9243 VINA +V C REF H V 14 Q CORE S2 A/D CORE C + PIN Q C C S1 S PAR VINA VINB –VREF Q Q C H1 S1 S VINB C – PIN
Figure 20. AD9243 Equivalent Functional Input Circuit
Q C S2 PAR
The addition of a differential input structure gives the user an
CH
additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily config- Figure 21. AD9243 Simplified Input Circuit ure the inputs for either single-ended operation or differential operation. The A/D’s input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. Specifically, the input to the A/D core is the difference of the voltages applied at the VINA and VINB input pins. –8– REV. A