Datasheet AD9243 (Analog Devices) - 10

AD9243
The input SHA of the AD9243 is optimized to meet the perfor- tion in THD performance as the input frequency increases. mance requirements for some of the most demanding commu- Similarly, note how the THD performance at lower frequencies nication, imaging, and data acquisition applications while becomes less sensitive to the common-mode voltage. As the maintaining low power dissipation. Figure 22 is a graph of the input frequency approaches dc, the distortion will be domi- full-power bandwidth of the AD9243, typically 40 MHz. Note nated by static nonlinearities such as INL and DNL. It is that the small signal bandwidth is the same as the full-power important to note that these dc static nonlinearities are inde- bandwidth. The settling time response to a full-scale stepped pendent of any RON modulation. input is shown in Figure 23 and is typically 80 ns to 0.0025%. The low input referred noise of 0.36 LSB’s rms is displayed via
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a grounded histogram and is shown in Figure 13.
0 –60 VCM = 1.0V –3 –70 THD – dB –6 –80 VCM = 2.5V AMPLITUDE – dB –9 –900.1 1 10 FREQUENCY – MHz –12
Figure 24. AD9243 THD vs. Frequency for VCM = 2.5 V and
1 10 100
1.0 V (A
FREQUENCY – MHz
IN = –0.5 dB, Input Span = 2.0 V p-p) Figure 22. Full-Power Bandwidth Due to the high degree of symmetry within the SHA topology, a significant improvement in distortion performance for differen- tial input signals with frequencies up to and beyond Nyquist can
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be realized. This inherent symmetry provides excellent cancella- tion of both common-mode distortion and noise. Also, the required input signal voltage span is reduced by a half which
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further reduces the degree of RON modulation and its effects on distortion. The optimum noise and dc linearity performance for either
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differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 5 V input span) and matched input impedance for VINA and VINB. Note that only a slight
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degradation in dc linearity performance exists between the 2 V and 5 V input span as specified in the AD9243 “DC SPECIFICATIONS.”
0 0 10 20 30 40 50 60 70 80
Referring to Figure 21, the differential SHA is implemented
SETTLING TIME – ns
using a switched-capacitor topology. Hence, its input imped- Figure 23. Settling Time ance and its subsequent effects on the input drive source should The SHA’s optimum distortion performance for a differential or be understood to maximize the converter’s performance. The single-ended input is achieved under the following two condi- combination of the pin capacitance, CPIN, parasitic capacitance tions: (1) the common-mode voltage is centered around mid CPAR, and the sampling capacitance, CS, is typically less than supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input 16 pF. When the SHA goes into track mode, the input source signal voltage span of the SHA is set at its lowest (i.e., 2 V input must charge or discharge the voltage stored on CS to the new span). This is due to the sampling switches, Q input voltage. This action of charging and discharging CS which S1, being CMOS switches whose R is approximately 4 pF, averaged over a period of time and for a ON resistance is very low but has some signal dependency which causes frequency dependent ac distortion given sampling frequency, FS, makes the input impedance ap- while the SHA is in the track mode. The R pear to have a benign resistive component (i.e., 83 kΩ at FS = ON resistance of a CMOS switch is typically lowest at its midsupply but increases 3.0 MSPS). However, if this action is analyzed within a sam- symmetrically as the input signal approaches either AVDD or pling period (i.e., T = <1/FS), the input impedance is dynamic AVSS. A lower input signal voltage span centered at midsupply due to the instantaneous requirement of charging and discharg- reduces the degree of R ing CS. A series resistor inserted between the input drive source ON modulation. and the SHA input as shown in Figure 25 provides the effective Figure 24 compares the AD9243’s THD vs. frequency perfor- isolation. mance for a 2 V input span with a common-mode voltage of 1 V and 2.5 V. Note the difference in the amount of degrada- REV. A –9–