Datasheet AD7862 (Analog Devices) - 9

AD7862
currents, as the resistor stage is followed by a high input applications, offset and full-scale error will have to be adjusted impedance stage of the track/hold amplifier. For the AD7862-10, to zero. R1 = 30 kΩ, R2 = 7.5 kΩ, and R3 = 10 kΩ. For the AD7862-3, Figure 4 shows a circuit that can be used to adjust the offset and R1 = R2 = 6.5 kΩ and R3 is open circuit. full-scale errors on the AD7862 (VA1 on the AD7862-10 version For the AD7862-10 and AD7862-3, the designed code transi- is shown for example purposes only). Where adjustment is tions occur on successive integer LSB values (i.e., 1 LSB, required, offset error must be adjusted before full-scale error. 2 LSBs, 3 LSBs . .). Output coding is twos complement This is achieved by trimming the offset of the op amp driving binary with 1 LSB = FS/4096. The ideal input/output transfer the analog input of the AD7862 while the input voltage is a function for the AD7862-10 and AD7862-3 is shown in Table I. 1/2 LSB below analog ground. The trim procedure is as follows: apply a voltage of –2.44 mV (–1/2 LSB) at VA1 (see Figure 4)
Table I. Ideal Input/Output Code Table for the AD7862-10/-3
and adjust the op amp offset voltage until the ADC output code flickers between 1111 1111 1111 and 0000 0000 0000.
Analog Inputl Digital Output Code Transition INPUT
+FSR/2 – 1 LSB2 011 . 110 to 011 . 111
RANGE =
±
10V V
+FSR/2 – 2 LSBs 011 . 101 to 011 . 110
1
+FSR/2 – 3 LSBs 011 . 100 to 011 . 101
R1
GND + 1 LSB 000 . 000 to 000 . 001
10k
Ω
R2
GND 111 . 111 to 000 . 000
500
Ω
VA1
GND – 1 LSB 111 . 110 to 111 . 111
R4
–FSR/2 + 3 LSBs 100 . 010 to 100 . 011
10k
Ω
AD7862*
–FSR/2 + 2 LSBs 100 . 001 to 100 . 010
R3 R5
–FSR/2 + 1 LSB 100 . 000 to 100 . 001
10k
Ω
10k
Ω
AGND
NOTES 1FSR is full-scale range = 20 V (AD7862-10) and = 5 V (AD7862-3) with REF IN = +2.5 V. 21 LSB = FSR/4096 = 4.883 mV (AD7862-10) and 1.22 mV (AD7862-3) with REF IN = +2.5 V.
*ADDITIONAL PINS OMITTED FOR CLARITY
The analog input section for the AD7862-2 contains no biasing Figure 4. Full-Scale Adjust Circuit resistors, and the VAX/BX pin drives the input to the multiplexer and track/hold amplifier circuitry directly. The analog input Gain error can be adjusted at either the first code transition range is 0 V to +2.5 V into a high impedance stage with an (ADC negative full scale) or the last code transition (ADC input current of less than 500 nA. This input is benign with no positive full scale). The trim procedures for both cases are as dynamic charging currents. Once again, the designed code follows: transitions occur on successive integer LSB values. Output
Positive Full-Scale Adjust
coding is straight (natural) binary with 1 LSB = FS/4096 = Apply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at VA1. Adjust 2.5 V/4096 = 0.61 mV. Table II shows the ideal input/output R2 until the ADC output code flickers between 0111 1111 1110 transfer function for the AD7862-2. and 0111 1111 1111.
Negative Full-Scale Adjust Table II. Ideal Input/Output Code Table for the AD7862-2
Apply a voltage of –9.9976 V (–FS + 1/2 LSB) at VA1 and adjust
Analog Input1 Digital Output Code Transition
R2 until the ADC output code flickers between 1000 0000 0000 and 1000 0000 0001. +FSR – 1 LSB2 111 . 110 to 111 . 111 An alternative scheme for adjusting full-scale error in systems +FSR – 2 LSB 111 . 101 to 111 . 110 that use an external reference is to adjust the voltage at the +FSR – 3 LSB 111 . 100 to 111 . 101 VREF pin until the full-scale error for any of the channels is GND + 3 LSB 000 . 010 to 000 . 011 adjusted out. The good full-scale matching of the channels will GND + 2 LSB 000 . 001 to 000 . 010 ensure small full-scale errors on the other channels. GND + 1 LSB 000 . 000 to 000 . 001 NOTES
TIMING AND CONTROL
1FSR is full-scale range and is 2.5 V for AD7862-2 with VREF = +2.5 V. Figure 5a shows the timing and control sequence required to 21 LSB = FSR/4096 and is 0.61 mV for AD7862-2 with VREF = +2.5 V. obtain optimum performance (Mode 1) from the AD7862. In the sequence shown, a conversion is initiated on the falling edge
OFFSET AND FULL-SCALE ADJUSTMENT
of CONVST. This places both track/holds into hold simulta- In most digital signal processing (DSP) applications, offset and neously, and new data from this conversion is available in the full-scale errors have little or no effect on system performance. output register of the AD7862 3.6 µs later. The BUSY signal Offset error can always be eliminated in the analog domain by indicates the end of conversion, and at this time the conversion ac coupling. Full-scale error effect is linear and does not cause results for both inputs are available to be read. A second problems as long as the input signal is within the full dynamic conversion is then initiated. If the multiplexer select A0 is low, range of the ADC. Invariably, some applications will require the the first and second read pulses after the first conversion accesses input signal to span the full analog input dynamic range. In such the result from channel A (VA1 and VA2 respectively). The third –8– REV. 0