Datasheet AD10242 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | Dual Channel, 12-Bit, 40 MSPS MCM A/D Converter with DC-Coupled Analog Input Signal Conditioning (AD9042 Core ADC) |
| 页数 / 页 | 16 / 3 |
| 修订版 | D |
| 文件格式/大小 | PDF / 453 Kb |
| 文件语言 | 英语 |
该数据表的模型线
文件文字版本
AD10242–SPECIFICATIONS Electrical Characteristics (AVCC = +5 V; AVEE = –5.0 V; DVCC = +5 V; applies to each ADC, unless otherwise noted.) Test Mil AD10242BZ/TZ Parameter Temp Level Subgroup Min Typ Max Unit
RESOLUTION 12 Bits DC ACCURACY No Missing Codes Full VI 1, 2, 3 Guaranteed Offset Error 25°C I 1 –0.5 ±0.05 +0.5 % FS Full VI 2, 3 –2.0 ±1.0 +2.0 % FS Offset Error Channel Match Full V ±0.1 % Gain Error1 25°C I 1 –1.0 ±0.5 +1.0 % FS Full VI 2, 3 –1.5 ±0.8 +1.5 % FS Gain Error Channel Match Full V ±0.1 % ANALOG INPUT (AIN) Input Voltage Range AIN1 Full I ±0.5 V AIN2 Full I ±1.0 V AIN3 Full I ±2 V Input Resistance AIN1 Full IV 12 99 100 101 Ω AIN2 Full IV 12 198 200 202 Ω AIN3 Full IV 12 396 400 404 Ω Input Capacitance2 25°C IV 12 0 4.0 7.0 pF Analog Input Bandwidth3 Full V 60 MHz ENCODE INPUT4, 5 Logic Compatibility TTL/CMOS Logic “1” Voltage Full I 1, 2, 3 2.0 5.0 V Logic “0” Voltage Full I 1, 2, 3 0 0.8 V Logic “1” Current (VINH = 5 V) Full I 1, 2, 3 625 800 µA Logic “0” Current (VINL = 0 V) Full I 1, 2, 3 –400 –300 µA Input Capacitance 25°C V 12 7.0 pF SWITCHING PERFORMANCE Maximum Conversion Rate6 Full VI 4, 5, 6 40 50 MSPS Minimum Conversion Rate6 Full V 12 5 MSPS Aperture Delay (tA) 25°C V 1.0 ns Aperture Delay Matching 25°C V ±2.0 ns Aperture Uncertainty (Jitter) 25°C V 1 ps rms ENCODE Pulsewidth High 25°C IV 12 12 10 ns ENCODE Pulsewidth Low 25°C IV 12 10 41 ns Output Delay (tOD) Full IV 12 10 12 14 ns SNR7 Analog Input @ 1.2 MHz 25°C V 68 dB @ 4.85 MHz 25°C I 4 63 66 dB Full II 5, 6 62 66 dB @ 9.9 MHz 25°C I 4 63 65 dB Full II 5, 6 62 65 dB @ 19.5 MHz 25°C I 4 60 63 dB Full II 5, 6 59 62 dB SINAD8 Analog Input @ 1.2 MHz 25°C V 67 dB @ 4.85 MHz 25°C I 4 62 65 dB Full II 5, 6 61 64 dB @ 9.9 MHz 25°C I 4 60 64 dB Full II 5, 6 60 63 dB @ 19.5 MHz 25°C I 4 58 61 dB Full II 5, 6 58 60 dB –2– REV. D Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS1 EXPLANATION OF TEST LEVELS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITION OF SPECIFICATIONS Analog Bandwidth Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Harmonic Distortion Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Overvoltage Recovery Time Power Supply Rejection Ratio Signal-to-Noise and Distortion (SINAD) Signal-to-Noise Ratio (SNR, without Harmonics) Spurious-Free Dynamic Range (SFDR) Transient Response Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR EQUIVALENT CIRCUITS Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD10242 Encoding the AD10242 Performance Improvements USING THE FLEXIBLE INPUT GROUNDING AND DECOUPLING Analog and Digital Grounding LAYOUT INFORMATION EVALUATION BOARD OUTLINE DIMENSIONS Ordering Guide Revision History
RESOLUTION 12 Bits DC ACCURACY No Missing Codes Full VI 1, 2, 3 Guaranteed Offset Error 25°C I 1 –0.5 ±0.05 +0.5 % FS Full VI 2, 3 –2.0 ±1.0 +2.0 % FS Offset Error Channel Match Full V ±0.1 % Gain Error1 25°C I 1 –1.0 ±0.5 +1.0 % FS Full VI 2, 3 –1.5 ±0.8 +1.5 % FS Gain Error Channel Match Full V ±0.1 % ANALOG INPUT (AIN) Input Voltage Range AIN1 Full I ±0.5 V AIN2 Full I ±1.0 V AIN3 Full I ±2 V Input Resistance AIN1 Full IV 12 99 100 101 Ω AIN2 Full IV 12 198 200 202 Ω AIN3 Full IV 12 396 400 404 Ω Input Capacitance2 25°C IV 12 0 4.0 7.0 pF Analog Input Bandwidth3 Full V 60 MHz ENCODE INPUT4, 5 Logic Compatibility TTL/CMOS Logic “1” Voltage Full I 1, 2, 3 2.0 5.0 V Logic “0” Voltage Full I 1, 2, 3 0 0.8 V Logic “1” Current (VINH = 5 V) Full I 1, 2, 3 625 800 µA Logic “0” Current (VINL = 0 V) Full I 1, 2, 3 –400 –300 µA Input Capacitance 25°C V 12 7.0 pF SWITCHING PERFORMANCE Maximum Conversion Rate6 Full VI 4, 5, 6 40 50 MSPS Minimum Conversion Rate6 Full V 12 5 MSPS Aperture Delay (tA) 25°C V 1.0 ns Aperture Delay Matching 25°C V ±2.0 ns Aperture Uncertainty (Jitter) 25°C V 1 ps rms ENCODE Pulsewidth High 25°C IV 12 12 10 ns ENCODE Pulsewidth Low 25°C IV 12 10 41 ns Output Delay (tOD) Full IV 12 10 12 14 ns SNR7 Analog Input @ 1.2 MHz 25°C V 68 dB @ 4.85 MHz 25°C I 4 63 66 dB Full II 5, 6 62 66 dB @ 9.9 MHz 25°C I 4 63 65 dB Full II 5, 6 62 65 dB @ 19.5 MHz 25°C I 4 60 63 dB Full II 5, 6 59 62 dB SINAD8 Analog Input @ 1.2 MHz 25°C V 67 dB @ 4.85 MHz 25°C I 4 62 65 dB Full II 5, 6 61 64 dB @ 9.9 MHz 25°C I 4 60 64 dB Full II 5, 6 60 63 dB @ 19.5 MHz 25°C I 4 58 61 dB Full II 5, 6 58 60 dB –2– REV. D Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS1 EXPLANATION OF TEST LEVELS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITION OF SPECIFICATIONS Analog Bandwidth Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Harmonic Distortion Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Overvoltage Recovery Time Power Supply Rejection Ratio Signal-to-Noise and Distortion (SINAD) Signal-to-Noise Ratio (SNR, without Harmonics) Spurious-Free Dynamic Range (SFDR) Transient Response Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR EQUIVALENT CIRCUITS Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD10242 Encoding the AD10242 Performance Improvements USING THE FLEXIBLE INPUT GROUNDING AND DECOUPLING Analog and Digital Grounding LAYOUT INFORMATION EVALUATION BOARD OUTLINE DIMENSIONS Ordering Guide Revision History