Datasheet AD10242 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Dual Channel, 12-Bit, 40 MSPS MCM A/D Converter with DC-Coupled Analog Input Signal Conditioning (AD9042 Core ADC) |
| 页数 / 页 | 16 / 8 — AD10242. N + 1. N + 2. N + 3. N + 4. N + 5. ENC. D11. TTL CLOCK. D10. f … |
| 修订版 | D |
| 文件格式/大小 | PDF / 453 Kb |
| 文件语言 | 英语 |
AD10242. N + 1. N + 2. N + 3. N + 4. N + 5. ENC. D11. TTL CLOCK. D10. f 10MHz. AIN. 1/2. tA = 1.0ns TYP. A 2. SHOWN. ENCODE. D1 D0. tOD = 12ns TYP. DIGITAL
该数据表的模型线
文件文字版本
AD10242 N N + 1 N + 2 N + 3 N + 4 N + 5 ENC D11 TTL CLOCK D10 f 10MHz ENC D9 AIN D8 3 D7 AIN 1/2 D6 AD10242 D5 tA = 1.0ns TYP A 2 IN D4 SHOWN D3 ENCODE 1 D2 AIN D1 D0 tOD = 12ns TYP DIGITAL N – 2 N – 1 N N + 1 N + 2 OUTPUTS ALL 5V SUPPLY PINS BYPASSED TO GND WITH A 0.1
F CAPACITOR
Figure 2. Equivalent Burn-In Circuit Figure 1. Timing Diagram
EQUIVALENT CIRCUITS A DV IN3 CC R4 200
⍀
AIN2 CURRENT R3 MIRROR 100
⍀
AIN1 R2 21
⍀
TO AD9632 R1 79
⍀
DVCC
Figure 3. Analog Input Stage
VREF D0–D11 AVCC AV AV CC CC R1 R1 17k
⍀
17k
⍀
CURRENT ENCODE ENCODE MIRROR TIMING R2 R2 CIRCUITS 8k
⍀
8k
⍀ Figure 5. Digital Output Stage Figure 4. Encode Inputs REV. D –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS1 EXPLANATION OF TEST LEVELS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITION OF SPECIFICATIONS Analog Bandwidth Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Harmonic Distortion Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Overvoltage Recovery Time Power Supply Rejection Ratio Signal-to-Noise and Distortion (SINAD) Signal-to-Noise Ratio (SNR, without Harmonics) Spurious-Free Dynamic Range (SFDR) Transient Response Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR EQUIVALENT CIRCUITS Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD10242 Encoding the AD10242 Performance Improvements USING THE FLEXIBLE INPUT GROUNDING AND DECOUPLING Analog and Digital Grounding LAYOUT INFORMATION EVALUATION BOARD OUTLINE DIMENSIONS Ordering Guide Revision History
F CAPACITOR
Figure 2. Equivalent Burn-In Circuit Figure 1. Timing Diagram
EQUIVALENT CIRCUITS A DV IN3 CC R4 200
⍀
AIN2 CURRENT R3 MIRROR 100
⍀
AIN1 R2 21
⍀
TO AD9632 R1 79
⍀
DVCC
Figure 3. Analog Input Stage
VREF D0–D11 AVCC AV AV CC CC R1 R1 17k
⍀
17k
⍀
CURRENT ENCODE ENCODE MIRROR TIMING R2 R2 CIRCUITS 8k
⍀
8k
⍀ Figure 5. Digital Output Stage Figure 4. Encode Inputs REV. D –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS1 EXPLANATION OF TEST LEVELS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITION OF SPECIFICATIONS Analog Bandwidth Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Harmonic Distortion Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Overvoltage Recovery Time Power Supply Rejection Ratio Signal-to-Noise and Distortion (SINAD) Signal-to-Noise Ratio (SNR, without Harmonics) Spurious-Free Dynamic Range (SFDR) Transient Response Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR EQUIVALENT CIRCUITS Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD10242 Encoding the AD10242 Performance Improvements USING THE FLEXIBLE INPUT GROUNDING AND DECOUPLING Analog and Digital Grounding LAYOUT INFORMATION EVALUATION BOARD OUTLINE DIMENSIONS Ordering Guide Revision History