Datasheet AD7854, AD7854L (Analog Devices) - 4

AD7854/AD7854L TIMING SPECIFICATIONS1 (AVDD = DVDD = +3.0 V to +5.5 V; fCLKIN = 4 MHz for AD7854 and 1.8 MHz for AD7854L; TA = TMIN to TMAX, unless otherwise noted) Limit at TMIN, TMAX (A, B, S Versions) Parameter 5 V 3 V Units Description
f 2 CLKIN 500 500 kHz min Master Clock Frequency 4 4 MHz max 1.8 1.8 MHz max L Version t 3 1 100 100 ns min CONVST Pulsewidth t2 50 90 ns max CONVST to BUSY ↑ Propagation Delay tCONVERT 4.5 4.5 µs max Conversion Time = 18 tCLKIN 10 10 µs max L Version 1.8 MHz CLKIN. Conversion Time = 18 tCLKIN t3 15 15 ns min HBEN to RD Setup Time t4 5 5 ns min HBEN to RD Hold Time t5 0 0 ns min CS to RD to Setup Time t6 0 0 ns min CS to RD Hold Time t7 55 70 ns min RD Pulsewidth t 4 8 50 50 ns max Data Access Time After RD t 5 9 5 5 ns min Bus Relinquish Time After RD 40 40 ns max t10 60 70 ns min Minimum Time Between Reads t11 0 0 ns min HBEN to WR Setup Time t12 5 5 ns max HBEN to WR Hold Time t13 0 0 ns min CS to WR Setup Time t14 0 0 ns max CS to WR Hold Time t15 55 70 ns min WR Pulsewidth t16 10 10 ns min Data Setup Time Before WR t17 5 5 ns min Data Hold Time After WR t 4 18 1/2 tCLKIN 1/2 tCLKIN ns min New Data Valid Before Falling Edge of BUSY t19 50 70 ns min HBEN High Pulse Duration t20 50 70 ns min HBEN Low Pulse Duration t21 40 60 ns min Propagation Delay from HBEN Rising Edge to Data Valid t22 40 60 ns min Propagation Delay from HBEN Falling Edge to Data Valid t23 2.5 tCLKIN 2.5 tCLKIN ns max CS↑ to BUSY ↑ in Calibration Sequence t 6 CAL 31.25 31.25 ms typ Full Self-Calibration Time, Master Clock Dependent (125013 tCLKIN) t 6 CAL1 27.78 27.78 ms typ Internal DAC Plus System Full-Scale Cal Time, Master Clock Dependent (111124 tCLKIN) t 6 CAL2 3.47 3.47 ms typ System Offset Calibration Time, Master Clock Dependent (13889 tCLKIN) NOTES 1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2Mark/Space ratio for the master clock input is 40/60 to 60/40. 3The CONVST pulsewidth here only applies for normal operation. When the part is in power-down mode, a different CONVST pulsewidth applies (see Power-Down section). 4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 5t9 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 9, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 6The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to the 1.8 MHz master clock. Specifications subject to change without notice. –4– REV. B