Datasheet AD7721 (Analog Devices) - 10

AD7721 Input Circuits
The choice of the filter corner frequency will depend on the The purpose of antialiasing filters is to attenuate out of band amount of rolloff which is acceptable in-band and the attenua- signals that would otherwise be mixed down into the signal tion which is required at the first image frequency. For example, band. With traditional ADCs, high order filters using expensive when fCLK = 15 MHz, REXT = 50 Ω, CEXT = 7.84 nF, the in- high tolerance passive components are often required to per- band rolloff is 1 dB and the attenuation at the first image fre- form this function. Using oversampling, as employed on the quency is 31.1 dB. Increasing the size of the external resistor AD7721, this problem is considerably alleviated. Figure 4a above 50 Ω can cause increased distortion due to nonlinear shows the digital filter frequency response. Due to the sampling charging currents. nature of the digital filter, the passband is repeated about the operating clock frequency and at multiples of the clock fre-
REXT
quency. Out of band signals coincident with any of the filter
VIN1
images are mixed down into the passband. Figure 4b shows the
CEXT ANALOG AD7721
frequency response of the antialias filter required to provide a
INPUT REXT
particular level of attenuation at the first image frequency. Fig-
VIN2
ure 4c shows the frequency response of the antialias filter re-
CEXT
quired to achieve the same level of attenuation with a traditional ADC. The much smaller transition band can only be achieved with a very high order filter. Figure 5. Simple RC Antialiasing Filter Figure 6 shows a simple circuit that can be used to drive the
0dB
AD7721 in unipolar mode. The input of the AD7721 is sampled by a 1.6 pF input capacitor. This creates glitches on the input of the modulator. By placing the RC filter directly before the AD7721, rather than before the operational amplifier, these
fCLK 2fCLK 3fCLK
glitches are prevented from being fed back into the operational amplifier and creating distortion. The resistor in this diagram, a. Digital Filter Frequency Response as well as creating a pole for the antialias filter, also isolates the storage capacitor from the operational amplifier which may
OUTPUT DATA RATE
otherwise be unstable.
0dB ANTIALIAS FILTER RESPONSE REQUIRED ATTENUATION ANALOG REXT INPUT VIN1 CEXT AD7721 fCLK COMMON MODE VIN2
b. Frequency Response of Antialias Filter (AD7721)
VOLTAGE ANTIALIAS FILTER
Figure 6. Antialiasing Circuits
RESPONSE OUTPUT DATA RATE 0dB
A suitable operational amplifier is the AD847 if a ± 15 V power
REQUIRED
supply is available. If only a +5 V power supply is available, the
ATTENUATION
AD820 can be used. This operational amplifier can be used with input bandwidths up to 80 kHz. However, the slew rate of this operational amplifier limits its performance to 80 kHz. Above c. Frequency Response of Antialias Filter (Traditional ADC) this frequency, the performance of the AD820 degrades. Figure 4. Frequency Response of Antialiasing Filters For both filters, the capacitor CEXT should have a low tempera- Figure 5 shows a simple antialiasing filter which can be used ture coefficient and should be linear to avoid distortion. with the AD7721. The –3 dB corner frequency (f Polypropylene or polystyrene capacitors are suitable. 3 dB) of the antialias filter is given by Equation 1, and the attenuation of the
Offset and Gain Calibration
filter is given by Equation 2. Attenuation at the first image A calibration of offset and gain errors can be performed in both frequency is given by Equation 3. serial and parallel modes by initiating a calibration cycle. During f this cycle, offset and gain registers in the filter are loaded with 3 dB = 1/(2 π REXT CEXT) Equation 1 values representing the dc offset of the analog modulator and a   modulator gain correction factor. In normal operation, the offset Attenuation = 20 log 1 / 1 + ( f / f )2 3 dB   Equation 2 register is subtracted from the digital filter output and this result is then multiplied by the gain correction factor to obtain an offset and gain corrected final result. Attenuation (First Image) = During the calibration cycle, in which the offset of the analog   modulator is evaluated, the inputs to the modulator are shorted 20log 1/ 1+ ( 0.986 f )2 CLK / f 3 dB   Equation 3 together internally. When the modulator and digital filter settle, the average of 8 output results is calculated and stored in the offset register. The gain of the modulator is determined by REV. A –9–