Datasheet AD7858, AD7858L (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 3 V to 5 V Single Supply, 200 kSPS, 8-Channel, 12-Bit, Serial Sampling ADC |
| 页数 / 页 | 32 / 5 — AD7858/AD7858L. TYPICAL TIMING DIAGRAMS. 1.6mA. IOL. OUTPUT. +2.1V. PIN. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 309 Kb |
| 文件语言 | 英语 |
AD7858/AD7858L. TYPICAL TIMING DIAGRAMS. 1.6mA. IOL. OUTPUT. +2.1V. PIN. 100pF. 200. IOH. tCONVERT = 4.6. s MAX, 10. s MAX FOR L VERSION
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AD7858/AD7858L TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams for
1.6mA IOL
serial Interface Mode 2. The reading and writing occurs after conversion in Figure 2, and during conversion in Figure 3. To
TO OUTPUT +2.1V
attain the maximum sample rate of 100 kHz (AD7858L) or
PIN CL
200 kHz (AD7858), reading and writing must be performed
100pF
during conversion as in Figure 3. At least 400 ns acquisition
200
A IOH
time must be allowed (the time from the falling edge of BUSY to the next rising edge of CONVST) before the next conversion Figure 1. Load Circuit for Digital Output Timing begins to ensure that the part is settled to the 12-bit level. If the Specifications user does not want to provide the CONVST signal, the conver- sion can be initiated in software by writing to the control register.
tCONVERT = 4.6
s MAX, 10
s MAX FOR L VERSION t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V t1 CONVST (I/P) tCONVERT t2 BUSY (O/P) SYNC (I/P) t3 t t 9 11 1 5 6 16 SCLK (I/P) t4 t10 t t 12 6 t6 THREE-STATE THREE- DOUT (O/P) DB15 DB11 DB0 STATE t8 t7 DIN (I/P) DB15 DB11 DB0
Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
tCONVERT = 4.6
s MAX, 10
s MAX FOR L VERSION t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V t1 CONVST (I/P) tCONVERT t2 BUSY (O/P) SYNC (I/P) t3 t t 9 11 1 5 6 16 SCLK (I/P) t4 t10 t t 12 6 t6 THREE-STATE THREE- DOUT (O/P) DB15 DB11 DB0 STATE t8 t7 DIN (I/P) DB15 DB11 DB0
Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion) REV. B –5–
Figures 2 and 3 show typical read and write timing diagrams for
1.6mA IOL
serial Interface Mode 2. The reading and writing occurs after conversion in Figure 2, and during conversion in Figure 3. To
TO OUTPUT +2.1V
attain the maximum sample rate of 100 kHz (AD7858L) or
PIN CL
200 kHz (AD7858), reading and writing must be performed
100pF
during conversion as in Figure 3. At least 400 ns acquisition
200
A IOH
time must be allowed (the time from the falling edge of BUSY to the next rising edge of CONVST) before the next conversion Figure 1. Load Circuit for Digital Output Timing begins to ensure that the part is settled to the 12-bit level. If the Specifications user does not want to provide the CONVST signal, the conver- sion can be initiated in software by writing to the control register.
tCONVERT = 4.6
s MAX, 10
s MAX FOR L VERSION t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V t1 CONVST (I/P) tCONVERT t2 BUSY (O/P) SYNC (I/P) t3 t t 9 11 1 5 6 16 SCLK (I/P) t4 t10 t t 12 6 t6 THREE-STATE THREE- DOUT (O/P) DB15 DB11 DB0 STATE t8 t7 DIN (I/P) DB15 DB11 DB0
Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
tCONVERT = 4.6
s MAX, 10
s MAX FOR L VERSION t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V t1 CONVST (I/P) tCONVERT t2 BUSY (O/P) SYNC (I/P) t3 t t 9 11 1 5 6 16 SCLK (I/P) t4 t10 t t 12 6 t6 THREE-STATE THREE- DOUT (O/P) DB15 DB11 DB0 STATE t8 t7 DIN (I/P) DB15 DB11 DB0
Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion) REV. B –5–