Datasheet AD7853, AD7853L (Analog Devices) - 5

AD7853/AD7853L TYPICAL TIMING DIAGRAMS I
Figures 2 and 3 show typical read and write timing diagrams.
1.6mA OL
Figure 2 shows the reading and writing after conversion in In- terface Modes 2 and 3. To attain the maximum sample rate of 100 kHz (AD7853L) or 200 kHz (AD7853) in Interface Modes
TO OUTPUT +2.1V
2 and 3, reading and writing must be performed during conver-
PIN C
sion. Figure 3 shows the timing diagram for Interface Modes 4
L 100pF
and 5 with sample rate of 100 kHz (AD7853L) or 200 kHz (AD7853). At least 400 ns acquisition time must be allowed
200
m
A IOH
(the time from the falling edge of BUSY to the next rising edge of CONVST) before the next conversion begins to ensure that Figure 1. Load Circuit for Digital Output Timing the part is settled to the 12-bit level. If the user does not want to Specifications provide the CONVST signal, the conversion can be initiated in software by writing to the control register.
POLARITY PIN LOGIC HIGH t CONVERT = 4.6
m
s MAX, 10
m
s FOR L VERSION t t 1 = 100 ns MIN, t5 = 50/90 ns MAX 5V/3V, t7 = 40/60 ns MIN 5V/3V 1 CONVST (I/P) tCONVERT t2 BUSY (O/P) SYNC (I/P) t t 3 t 11 9 1 5 6 16 SCLK (I/P) t t 10 5 t t 12 t6 6 THREE- THREE- DOUT (O/P) DB15 DB11 DB0 STATE STATE t7 t8 DB15 DB11 DB0
Figure 2. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
POLARITY PIN LOGIC HIGH t CONVERT = 4.6
m
s MAX, 10
m
s FOR L VERSION t t 1 = 100 ns MIN, t5 = 50/90 ns MAX 5V/3V, t7 = 40/60 ns MIN 5V/3V 1 CONVST (I/P) tCONVERT t2 BUSY (O/P) SYNC (O/P) t4 t t 9 11 1 5 6 16 SCLK (O/P) t10 t5 t t 6 12 THREE- THREE- DOUT (O/P) DB15 DB11 DB0 STATE STATE t7 t8 DIN (I/P) DB15 DB11 DB0
Figure 3. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5) REV. B –5–