Datasheet AD876 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 10-Bit 20 MSPS 160 mW CMOS A/D Converter |
| 页数 / 页 | 17 / 4 — AD876 |
| 修订版 | B |
| 文件格式/大小 | PDF / 374 Kb |
| 文件语言 | 英语 |
AD876
该数据表的模型线
文件文字版本
AD876 (T DIGITAL SPECIFICATIONS MIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +3.3 V, VREFT = +4.0 V, VREFB = +2.0 V, fCLOCK = 20 MSPS, CL = 20 pF unless otherwise noted) AD876 Parameter Symbol DRVDD Min Typ Max Units
LOGIC INPUT High Level Input Voltage VIH 3.0 2.4 V 5.0 4.0 V 5.25 4.2 V Low Level Input Voltage VIL 3.0 0.6 V 5.0 1.0 V 5.25 1.05 V High Level Input Current IIH 5.0 –10 +10 µA Low Level Input Current IIL 5.0 –50 +50 µA Low Level Input Current (CLK Only) IIL 5.0 –10 +10 µA Input Capacitance CIN 5 pF LOGIC OUTPUTS High Level Output Voltage VOH (IOH = 50 µA) 3.0 2.4 V 5.0 3.8 V (IOH = 0.5 mA) 5.0 2.4 V Low Level Output Voltage VOL (IOL = 50 µA) 3.6 0.7 V 5.25 1.05 V (IOL = 0.6 mA) 5.25 0.4 V Output Capacitance COUT 5 pF Output Leakage Current IOZ –10 10 µA Specifications subject to change without notice.
TIMING SPECIFICATIONS Symbol Min Typ Max Units
Maximum Conversion Rate1 20 MHz Clock Period tC 50 ns Clock High tCH 23 25 ns Clock Low tCL 23 25 ns Output Delay tOD 10 20 ns Pipeline Delay (Latency) 3.5 Clock Cycles Aperture Delay Time 4 ns Aperture Jitter 22 ps NOTE 1Conversion rate is operational down to 10 kHz without degradation in specified performance.
SAMPLE N SAMPLE N+1 SAMPLE N+2 AIN t t CH CL CLK t t C OD OUT DATA N-4 DATA N-3 DATA N-2 DATA N-1 DATA N
Figure 1. Timing Diagram REV. B –3–
LOGIC INPUT High Level Input Voltage VIH 3.0 2.4 V 5.0 4.0 V 5.25 4.2 V Low Level Input Voltage VIL 3.0 0.6 V 5.0 1.0 V 5.25 1.05 V High Level Input Current IIH 5.0 –10 +10 µA Low Level Input Current IIL 5.0 –50 +50 µA Low Level Input Current (CLK Only) IIL 5.0 –10 +10 µA Input Capacitance CIN 5 pF LOGIC OUTPUTS High Level Output Voltage VOH (IOH = 50 µA) 3.0 2.4 V 5.0 3.8 V (IOH = 0.5 mA) 5.0 2.4 V Low Level Output Voltage VOL (IOL = 50 µA) 3.6 0.7 V 5.25 1.05 V (IOL = 0.6 mA) 5.25 0.4 V Output Capacitance COUT 5 pF Output Leakage Current IOZ –10 10 µA Specifications subject to change without notice.
TIMING SPECIFICATIONS Symbol Min Typ Max Units
Maximum Conversion Rate1 20 MHz Clock Period tC 50 ns Clock High tCH 23 25 ns Clock Low tCL 23 25 ns Output Delay tOD 10 20 ns Pipeline Delay (Latency) 3.5 Clock Cycles Aperture Delay Time 4 ns Aperture Jitter 22 ps NOTE 1Conversion rate is operational down to 10 kHz without degradation in specified performance.
SAMPLE N SAMPLE N+1 SAMPLE N+2 AIN t t CH CL CLK t t C OD OUT DATA N-4 DATA N-3 DATA N-2 DATA N-1 DATA N
Figure 1. Timing Diagram REV. B –3–