Datasheet AD876 (Analog Devices) - 8

AD876 1 PIPELINE DELAY (LATENCY)
The number of clock cycles between conversion initiation and
HARMONICS (dBc) 2ND –68.02 6TH –77.74
the associated output data being made available. New output
3RD –72.85 7TH –75.62 4TH –70.68 8TH –75.98
data is provided every clock cycle.
5TH –78.09 9TH –81.20 REFERENCE TOP/BOTTOM OFFSET THD = –64.12 SNR = 48.73
Resistance between the reference input and comparator input
SINAD = 48.61
tap points causes offset errors. These errors can be nulled out
SFDR = –68.02
by using the force-sense connection as shown in the Reference Input section.
2 4 3 6 7 8 5 9 THEORY OF OPERATION
The AD876 implements a pipelined multistage architecture to achieve high sample rate with low power. The AD876 distrib- utes the conversion over several smaller A/D subblocks, refining Figure 9. AD876JR-8 Typical FFT (fIN = 3.58 MHz, the conversion with progressively higher accuracy as it passes AIN = –0.5 dB, fCLOCK = 20 MSPS) the results from stage to stage. As a consequence of the distrib-
1
uted conversion, the AD876 requires a small fraction of the 1023 comparators used in a traditional flash type A/D. A sample-and-
HARMONICS (dBc)
hold function within each of the stages permits the first stage to
2ND –68.91 6TH –80.55 3RD –73.92 7TH –82.02
operate on a new input sample while the second and third stages
4TH –68.67 8TH –81.02
operate on the two preceding samples.
5TH –73.26 9TH –88.94 THD = –64.24 APPLYING THE AD876 SNR = 55.71 SINAD = 55.14 DRIVING THE ANALOG INPUT SFDR = –68.67
Figure 11 shows the equivalent analog input of the AD876, a
2 4
sample-and-hold amplifier (SHA). Bringing CLK to a logic low
5 3
level closes Switches 1 and 2 and opens Switch 3. The input
6 8 7
source connected to AIN must charge capacitor CH during this
9
time. When CLK transitions from logic “low” to logic “high,” Switch 1 opens first, placing the SHA in hold mode. Switch 2 opens subsequently. Switch 3 then closes, connects the feed- Figure 10. AD876 Typical FFT (fIN = 3.58 MHz, AIN = –0.5 dB, back loop around the op amp, and forces the output of the op fCLOCK = 20 MSPS) amp to equal the voltage stored on CH. When CLK transitions from logic “high” to logic “low”, Switch 3 opens first. Switch 2
DEFINITIONS OF SPECIFICATIONS
closes and reconnects the input to C
INTEGRAL NONLINEARITY (INL)
H. Finally, Switch 1 closes and places the SHA in track mode. Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale”. The The structure of the input SHA places certain requirements on point used as “zero” occurs 1/2 LSB before the first code transi- the input drive source. The combination of the pin capacitance, tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last CP, and the hold capacitance, CH, is typically less than 5 pF. code transition. The deviation is measured from the center of The input source must be able to charge or discharge this ca- each particular code to the true straight line. pacitance to 10-bit accuracy in one half of a clock cycle. When the SHA goes into track mode, the input source must charge or
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
discharge capacitor CH from the voltage already stored on CH
CODES)
(the previously captured sample) to the new voltage. In the An ideal ADC exhibits code transitions that are exactly 1 LSB worst case, a full-scale voltage step on the input, the input apart. DNL is the deviation from this ideal value. It is often source must provide the charging current through the RON (50 Ω) specified in terms of the resolution for which no missing codes of Switch 2 and quickly settle (within 1/2 CLK period). This (NMC) are guaranteed. situation corresponds to driving a low input impedance. On the other hand, when the source voltage equals the value previously
OFFSET ERROR
stored on CH, the hold capacitor requires no input current and The first transition should occur at a level 1/2 LSB above the equivalent input impedance is extremely high. “zero.” Offset is defined as the deviation of the actual first code Adding series resistance between the output of the source and transition from that point. the AIN pin reduces the drive requirements placed on the source. Figure 12 shows this configuration. The bandwidth of
GAIN ERROR
the particular application limits the size of this resistor. To The first code transition should occur for an analog value 1/2 LSB maintain the performance outlined in the data sheet specifica- above nominal negative full scale. The last transition should tions, the resistor should be limited to 200 Ω or less. For appli- occur for an analog value 1 1/2 LSB below the nominal positive cations with signal bandwidths less than 10 MHz, the user may full scale. Gain error is the deviation of the actual difference increase the size of the series resistor proportionally. Alterna- between first and last code transitions and the ideal difference tively, adding a shunt capacitance between the AIN pin and between the first and last code transitions. REV. B –7–