Datasheet AD7716 (Analog Devices) - 10

AD7716 GENERAL DESCRIPTION
The output of the comparator provides the digital input for the The AD7716 is a 4-channel 22-bit A/D converter with on-chip 1-bit DAC, so the system functions as a negative feedback loop digital filtering, intended for the measurement of wide dynamic which minimizes the difference signal. The digital data that rep- range, low frequency signals such as those representing ECG, resents the analog input voltage is in the duty cycle of the pulse EEG, chemical, physical or biological processes. It contains train appearing at the output of the comparator. It can be re- four sigma delta ADCs, a clock oscillator and a serial communi- trieved as a parallel binary data word using a digital filter. cations port.
C CLOCK
Each of the analog input signals to the AD7716 is continuously
R
sampled at a rate determined by the frequency of the master
AIN EN TO
clock, CLKIN. Four sigma-delta modulators convert the
DIGITAL
sampled signals into digital pulse trains whose duty cycles con-
FILTER INTEGRATOR STROBED
tain the digital information. These are followed by low-pass fil-
COMPARATOR R
ters to process the output of the modulators and update the
+VREF
output register at a maximum rate of 2.2 kHz. The output data
–VREF
can be read from the serial port at any rate up to this.
1-BIT DAC THEORY OF OPERATION
The general block diagram of a delta-sigma ADC is shown in Figure 5. First Order Modulator Figure 5. It contains the following elements: Sigma-delta ADCs are generally described by the order of the 1. Continuously Sampling Integrator analog low-pass filter. A simple example of a first order sigma- 2. A Differential Amplifier or Subtracter delta ADC is shown in Figure 5. This contains only a first- order low-pass filter or integrator. 3. A 1-Bit A/D Converter (Comparator) The AD7716 uses a second-order sigma-delta modulator and a 4. A 1-Bit DAC digital filter that provides a rolling average of the sampled out- 5. A Digital Low-Pass Filter put. After power-up or if there is a step change in the input voltage, there is a settling time before valid data is obtained. In operation, the sampled analog signal is fed to the subtracter, along with the output of the 1-bit DAC. The filtered difference
DIGITAL FILTERING
signal is fed to the comparator, whose output samples the differ- The AD7716’s digital filter behaves like an analog filter, with a ence signal at a frequency many times that of the analog signal few minor differences. frequency (oversampling). First, since digital filtering occurs after the A-to-D conversion Oversampling is fundamental to the operation of delta-sigma process, it can remove noise injected during the conversion pro- ADCs. Using the quantization noise formula for an ADC: cess. Analog filtering cannot do this. SNR = (6.02 3 number of bits + 1.76) dB, On the other hand, analog filtering can remove noise super- a 1-bit ADC or comparator yields an SNR of 7.78 dB. imposed on the analog signal before it reaches the ADC. Digital When operating with a master clock of 8 MHz, the AD7716 filtering cannot do this and noise peaks riding on signals near samples the input signal at 570 kHz, which spreads the quanti- full scale have the potential to saturate the analog modulator zation noise from 0 kHz to 285 kHz. Since the specified analog and digital filter, even though the average value of the signal is input bandwidth of the AD7716 is only 584 Hz maximum (it within limits. If noise signals cause the input signal to exceed can be programmed to be lower), the noise energy in this band- the specified range, consideration should be given to analog in- width would be only 1/488 of the total quantization noise, as- put filtering, or to reducing the gain in the input channel to suming that the noise energy was spread evenly throughout the bring the combination of signal and noise spike within the speci- spectrum. This very high sampling with respect to the input fied input range. bandwidth is known as oversampling, and the ratio of 488:1 is
Filter Characteristics
called the oversampling ratio. The noise is reduced still further The cutoff frequency of the digital filter is determined by bits by analog filtering in the modulator loop, which shapes the FC2, FC1 and FC0 in the control register (See Table IV). The quantization noise spectrum to move most of the noise energy to cutoff frequency of the filter is fCLKIN /(3.81 3 14 3 256 3 2N), frequencies above 584 Hz. The SNR performance in the 0 Hz where N is the decimal equivalent of FC2, FC1, FC0. At the to 584 Hz range is conditioned to the 99 dB level in this fashion maximum clock frequency of 8 MHz, with all 0s loaded to FC2, (see Table I). As the programmed bandwidth is reduced, the FC1, FC0, the cutoff frequency of the filter is 584 Hz and the oversampling ratio increases and the usable dynamic range also data update rate is 2232 Hz. increases. Thus, for example, with a programmed bandwidth Since the AD7716 contains low-pass filtering, there is a settling of 73 Hz, the oversampling ratio is 3904:1, and the usable dy- time associated with step function inputs, and data will be in- namic range is 108 dB which corresponds to greater than 17-bit valid after a step change until the settling time has elapsed. The resolution. REV. A –9–