Datasheet AD7713 (Analog Devices) - 9

AD7713 Pin No. Mnemonic Function
16 RTD2 Constant Current Output. A nominal 200 µA constant current is provided at this pin, which can be used as the excitation current for RTDs. This current can be turned on or off via the control register. This second current can be used to eliminate lead resistanced errors in 3-wire RTD configurations. 17 AIN3 Analog Input Channel 3. High level analog input that accepts an analog input voltage range of 4 ⫻ VREF/GAIN. At the nominal VREF of 2.5 V and a gain of 1, the AIN3 input voltage range is 0 V to ± 10 V. 18 AGND Ground Reference Point for Analog Circuitry. 19 TFS Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word is written to the part. 20 RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the self- clocking mode, both the SCLK and SDATA lines become active after RFS goes low. In the external clocking mode, the SDATA line becomes active after RFS goes low. 21 DRDY Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin will return high upon completion of transmission of a full output word. DRDY is also used to indicate when the AD7713 has completed its on-chip calibration sequence. 22 SDATA Serial Data. Input/output with serial data being written to either the control register or the calibration regis- ters and serial data being accessed from the control register, calibration registers, or the data register. During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is low). Dur- ing a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low. The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs. 23 DVDD Digital Supply Voltage, 5 V. DVDD should not exceed AVDD by more than 0.3 V in normal operation. 24 DGND Ground Reference Point for Digital Circuitry.
TERMINOLOGY Positive Full-Scale Overrange Integral Nonlinearity
Positive full-scale overrange is the amount of overhead available This is the maximum deviation of any code from a straight line to handle input voltages on AIN1(+) and AIN2(+) inputs passing through the endpoints of the transfer function. The greater than (AIN1(–) + VREF/GAIN) or on AIN3 of greater endpoints of the transfer function are zero scale (not to be con- than 4 ⫻ VREF/GAIN (for example, noise peaks or excess voltages fused with bipolar zero), a point 0.5 LSB below the first code due to system gain errors in system calibration routines) without transition (000...000 to 000...001) and full scale, a point 0.5 LSB introducing errors due to overloading the analog modulator or above the last code transition (111...110 to 111...111). The error to overflowing the digital filter. is expressed as a percentage of full scale.
Negative Full-Scale Overrange Positive Full-Scale Error
This is the amount of overhead available to handle voltages on Positive full-scale error is the deviation of the last code transition AIN1(+) and AIN2(+) below (AIN1(–) – VREF/GAIN) without (111...110 to 111...111) from the ideal input full-scale voltage. overloading the analog modulator or overflowing the digital filter. For AIN1(+) and AIN2(+), the ideal full-scale input voltage is (AIN1(–) + V
Offset Calibration Range
REF/GAIN – 3/2 LSBs), where AIN(–) is either AIN1(–) or AIN2(–) as appropriate; for AIN3, the ideal full-scale In the system calibration modes, the AD7713 calibrates its offset voltage is 4 ⫻ V with respect to the analog input. The offset calibration range REF/GAIN – 3/2 LSBs. Positive full-scale error applies to both unipolar and bipolar analog input ranges. specification defines the range of voltages that the AD7713 can accept and still calibrate offset accurately.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
Full-Scale Calibration Range
from the ideal voltage. For AIN1(+) and AIN2(+), the ideal This is the range of voltages that the AD7713 can accept in the input voltage is (AIN1(–) + 0.5 LSB); for AIN3, the ideal input system calibration mode and still calibrate full scale correctly. is 0.5 LSB when operating in the unipolar mode.
Input Span
In system calibration schemes, two voltages applied in sequence
Bipolar Zero Error
This is the deviation of the midscale transition (0111 ... 111 to to the AD7713’s analog input define the analog input range. The 1000 ... 000) from the ideal input voltage. For AIN1(+) and input span specification defines the minimum and maximum AIN2(+), the ideal input voltage is (AIN1(–) – 0.5 LSB); AIN3 input voltages from zero to full scale that the AD7713 can accept can accommodate only unipolar input ranges. and still calibrate gain accurately.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal input voltage. For AIN1(+) and AIN2(+), the ideal input volt- age is (AIN1(–) – VREF/GAIN + 0.5 LSB); AIN3 can only accommodate unipolar input ranges. –8– REV. D Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION TERMINOLOGY Integral Nonlinearity Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span CONTROL REGISTER (24 BITS) Filter Selection (FS11 to FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burn Out Current RTD Excitation Currents Bipolar/Unipolar Inputs REFERENCE INPUT USING THE AD7713 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7713 to 8XC51 Interface AD7713 to 68HC11 Interface APPLICATIONS 4-Wire RTD Configurations 3-Wire RTD Configurations 4–20 mA Loop OTHER 24-BIT SIGNAL CONDITIONING ADCS AVAILABLE FROM ANALOG DEVICES AD7710 AD7711 AD7712 OUTLINE DIMENSIONS Revision History