Datasheet AD7880 (Analog Devices) - 6

AD7880 CIRCUIT INFORMATION R
The AD7880 is a +5 V single supply 12-bit A/D converter. The
VINA
part requires no external components apart from a 2.5 MHz ex-
+
ternal clock and power supply decoupling capacitors. It contains
R
a 12-bit successive approximation ADC based on a fast-settling
VINB
voltage-output DAC, a high speed comparator and SAR, as well
–
as the necessary control logic. The charge balancing comparator used in the AD7880 provides the user with an inherent track-
VDAC
and-hold function. The ADC is specified to work with sampling rates up to 66 kHz. Figure 4. AD7880 Input Circuit
CONVERTER DETAILS
The AD7880 accommodates three separate input ranges, 0 to The AD7880 conversion cycle is initiated on the rising edge of VREF, 0 to 2 VREF and ± VREF. The input configurations corre- the CONVST pulse, as shown in the timing diagram of Figure sponding to these ranges are shown in Figures 5, 6 and 7. 1. The rising edge of the CONVST pulse places the track/hold With VREF = VDD and using a nominal VDD of +5 V, the input amplifier into “HOLD” mode. The conversion cycle then takes ranges are 0 V to 5 V, 0 V to 10 V and +5 V, as shown in between 26 and 28 clock periods. The maximum specified con- Table II. version time is 12 µs. This corresponds to a conversion cycle time of 28 clock periods with a CLKIN frequency of 2.5 MHz
Table II. Analog Input Ranges
and also includes internal propagation delays. During conver-
Analog Input Input Connections Connection
sion the BUSY output will remain low, and the output databus
Range VREF VINA VINB Diagram
drivers will be three-stated. When a conversion is completed, the BUSY output will go to a high level, and the result of the 0 V to +5 V VDD VIN VIN Figure 5 conversion can be read by bringing CS and RD low. 0 V to +10 V VDD VIN AGND Figure 6 The track/hold amplifier acquires a 12-bit input signal in 3 µs. ±5 V VDD VIN VREF Figure 7 The overall throughput time for the AD7880 is equal to the conversion time plus the track/hold acquisition time. For a 2.5 MHz input clock the throughput time is 15 µs.
SAMPLING R COMPARATOR V = 0 TO V IN REF V 0 TO VREF INA REFERENCE INPUT + R
For specified performance, it is recommended that the reference
– VINB
input be tied to VDD. The part, however, will operate with a ref- erence down to 2.5 V though with reduced performance specifi-
VREF VREF 12-BIT DAC
cations. Figure 3 shows a graph of signal-to-noise ratio (SNR)
AGND
versus VREF. VREF must not be allowed to go above VDD by more than 100 mV. Figure 5. 0 to VREF Unipolar Input Configuration
74 F = 51.2kHz SAMPLING S 72 R COMPARATOR F = 2.525kHz IN V = 0 TO 2V IN REF V 0 TO VREF T = 25 C INA A + R 70 – VINB 68 VREF – dBs VREF 12-BIT DAC 66 AGND SNR 64
Figure 6. 0 to 2 VREF Unipolar Input Configuration
62 SAMPLING R 60 COMPARATOR 2 3 4 5 V = V ± IN REF V 0 TO VREF V – Volts INA + REF R –
Figure 3. SNR vs. V
V
REF
INB VREF VREF 12-BIT DAC ANALOG INPUT AGND
The AD7880 has two analog input pins, VINA and VINB. Figure 4 shows the input circuitry to the ADC sampling comparator. The on-board attenuator network, made up of equal resistors, allows for various input ranges. Figure 7. ±VREF Bipolar Input Configuration REV. 0 –5–