AD7701IOL1.6mATOCALOUTPUT+2.1VCLKINPINCLt1t2t100pF3IOHSC1, SC2SC1, SC2 VALID200µASLEEP Figure 1. Load Circuit for Access Figure 2a. Calibration Control Timing Figure 2b. SLEEP Mode Timing Time and Bus Relinquish Time DRDYCSt12CSt11CSSCLKt15t13t16tt10HI-Z14DATASDATAHI-ZHI-ZHI-ZVALIDSDATADB15 DB14DB1DB0DATASDATAVALID Figure 3. SSC Mode Data Figure 4a. SEC Mode Data Hold Time Figure 4b. SEC Mode Timing Diagram Hold Time CLKINCSDRDYt7CSt8HI-ZtSCLK17tSCLK4t5ttt61819tSTART5HI-ZHI-ZHI-ZHI-ZSDATADB8DB9DB7STOP 1STOP 2SDATADB15DB14DB1DB0HIGH BYTELOW BYTE Figure 5. SSC Mode Timing Diagram Figure 6. AC Mode Timing Diagram DEFINITION OF TERMSBipolar Zero ErrorLinearity Error This is the deviation of the midscale transition (0111 . 111 to This is the maximum deviation of any code from a straight line 1000 . 000) from the ideal (AGND – 0.5 LSB) when operating passing through the endpoints of the transfer function. The in the Bipolar mode. It is expressed in microvolts. endpoints of the transfer function are zero scale (not to be Bipolar Negative Full-Scale Error confused with bipolar zero), a point 0.5 LSB below the first This is the deviation of the first code transition from the ideal code transition (000 . 000 to 000 . 001) and full scale, a (–V point 1.5 LSB above the last code transition (111 . 110 to REF + 0.5 LSB) when operating in the Bipolar mode. It is expressed in microvolts. 111 . 111). The error is expressed as a percentage of full scale. Positive Full-Scale OverrangeDifferential Linearity Error Positive full-scale overrange is the amount of overhead available This is the difference between any code’s actual width and the to handle input voltages greater than +V ideal (1 LSB) width. Differential linearity error is expressed in REF (for example, noise peaks or excess voltages due to system gain errors in system LSBs. A differential linearity specification of ± 1 LSB or less calibration routines) without introducing errors due to overloading guarantees monotonicity. the analog modulator or overflowing the digital filter. It is Positive Full-Scale Error expressed in millivolts. Positive full-scale error is the deviation of the last code transition Negative Full-Scale Overrange (111 . 110 to 111 . 111) from the ideal (VREF ± 3/2 LSBs). This is the amount of overhead available to handle voltages below It applies to both positive and negative analog input ranges and –V is expressed in microvolts. REF without overloading the analog modulator or overflowing the digital filter. Note that the analog input will accept negative Unipolar Offset Error voltage peaks even in the Unipolar mode. The overhead is Unipolar offset error is the deviation of the first code transition expressed in millivolts. from the ideal (AGND + 0.5 LSB) when operating in the Uni- polar mode. It is expressed in microvolts. REV. E –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS TIMING CHARACTERISTICS DEFINITION OF TERMS Linearity Error Differential Linearity Error Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span GENERAL DESCRIPTION THEORY OF OPERATION DIGITAL FILTERING FILTER CHARACTERISTICS USING THE AD7701 SYSTEM DESIGN CONSIDERATIONS CLOCKING ANALOG INPUT RANGES INPUT SIGNAL CONDITIONING Source Resistance Antialias Considerations VOLTAGE REFERENCE CONNECTIONS GROUNDING AND SUPPLY DECOUPLING ACCURACY AND AUTOCALIBRATION CALIBRATION RANGE POWER-UP AND CALIBRATION POWER SUPPLY SEQUENCING GROUNDING SINGLE-SUPPLY OPERATION SLEEP MODE DIGITAL INTERFACE Synchronous Self-Clocking Mode (SSC) Synchronous External Clock Mode (SEC) Asynchronous Communications (AC) Mode DIGITAL NOISE AND OUTPUT LOADING OUTLINE DIMENSIONS Revision History