Datasheet AD5686, AD5684 (Analog Devices) - 7

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Data Sheet AD5686/AD5684 DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and Figure 5. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 5. 1.62 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V Parameter1 Symbol Min Max Min Max Unit
SCLK Cycle Time t1 66 40 ns SCLK High Time t2 33 20 ns SCLK Low Time t3 33 20 ns SYNC to SCLK Falling Edge t4 33 20 ns Data Setup Time t5 5 5 ns Data Hold Time t6 5 5 ns SCLK Falling Edge to SYNC Rising Edge t7 15 10 ns Minimum SYNC High Time t8 60 30 ns SDO Data Valid from SCLK Rising Edge t9 45 30 ns SYNC Rising Edge to SCLK Falling Edge t10 15 10 ns SYNC Rising Edge to SDO Disable t11 60 60 ns 1 Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams 200µA IOL TO OUTPUT VOH (MIN) PIN CL 20pF
003
200µA IOH
10797- Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
t1 SCLK 24 48 t t t 8 2 7 t t t 3 10 4 SYNC t6 t5 SDIN DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC N + 1 t9 SDO DB23 DB0
004
UNDEFINED INPUT WORD FOR DAC N
10797- Figure 4. Daisy-Chain Timing Diagram Rev. C | Page 7 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE