Datasheet AD5383 (Analog Devices)

32-Channel, 3 V/5 V, Single-Supply, 12-Bit, dense DAC Data Sheet AD5383 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic Channel monitor INL error: ±1 LSB max Simultaneous output update via LDAC On-chip 1.25 V/2.5 V, 10 ppm/°C reference Clear function to user-programmable code Temperature range: –40°C to +85°C Amplifier boost mode to optimize slew rate Rail-to-rail output amplifier User programmable offset and gain adjust Power-down mode Toggle mode enables square wave generation Package type: 100-lead LQFP (14 mm × 14 mm) Thermal monitor User Interfaces Parallel APPLICATIONS Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible, Variable optical attenuators (VOA) featuring data readback) Level setting (ATE) I2C-compatible Optical microelectro-mechanical systems (MEMS) Robust 6.5 kV HBM and 2 kV FICDM ESD rating Control systems Instrumentation FUNCTIONAL BLOCK DIAGRAM DVDD (
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3) DGND (
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3) AVDD (
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4) AGND (
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4) DAC GND (
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4) REFGND REFOUT/REFIN SIGNAL GND (
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4) PD AD5383 1.25V/2.5V SER/PAR REFERENCE FIFO EN CS/(SYNC/AD0) WR/(DCEN/AD1) 12 12 12 12 INPUT DAC SDO DAC 0 REG 0 REG 0 VOUT0 DB11/(DIN/SDA) 12 m REG 0 DB10/(SCLK/SCL) FIFO 12 DB9/(SPI/I2C) c REG 0 R + DB8 R INTERFACE STATE CONTROL MACHINE 12 12 12 12 LOGIC + INPUT DAC DAC 1 DB0 CONTROL REG 1 REG 1 VOUT1 LOGIC A4 12 V m REG 1 OUT2 A0 12 c REG 1 R VOUT3 R REG 0 VOUT4 12 12 12 12 INPUT DAC V REG 1 OUT5 DAC 6 REG 6 REG 6 POWER-ON VOUT6 RESET RESET 12 m REG 6 BUSY 12 c REG 6 R R CLR 12 12 12 12 INPUT DAC VOUT0………VOUT31 DAC 7 REG 7 REG 7 VOUT7 12 MON_IN1 m REG 7 VOUT8 36-TO-1 12 MON_IN2 c REG 7 R MUX MON_IN3 R MON_IN4
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4 VOUT31 MON_OUT LDAC
03734-001 Figure 1.
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Document Outline Features Integrated Functions Applications Functional Block Diagram Table of Contents Revision History General Description Specifications AD5383-5 Specifications AD5383-3 Specifications AC Characteristics9F Timing Characteristics Serial Interface Timing I2C Serial Interface Timing Parallel Interface Timing Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Channel Monitor Function Hardware Functions Reset Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down Interfaces DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer START and STOP Conditions Repeated START Conditions Acknowledge Bit (ACK) AD5383 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pins A4 to A0 Pins DB11 to DB0 Microprocessor Interfacing Parallel Interface AD5383 to MC68HC11 AD5383 to PIC16C6x/7x AD5383 to 8051 AD5383 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit Channel Monitor Function Toggle Mode Function Thermal Monitor Function Optical Attenuators Utilizing the FIFO Outline Dimensions Ordering Guide