Datasheet AD5381 (Analog Devices) - 8

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Data Sheet AD5381 AD5381-3 S PECIFICATIONS
AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2. Parameter AD5381-31 Unit Test Conditions/Comments
ACCURACY Output unloaded Resolution 12 Bits Relative Accuracy2 (INL) ±1 LSB max Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic over temperature Zero-Scale Error 4 mV max Offset Error ±4 mV max Measured at Code 16 in the linear region Offset Error TC ±5 µV/°C typ Gain Error ±0.05 % FSR max At 25 °C ±0.1 % FSR max TMIN to TMAX Gain Temperature Coefficient3 2 ppm FSR/°C typ DC Crosstalk3 1 LSB max REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage 1.25 V ±1% for specified performance DC Input Impedance 1 MΩ min Typically 100 MΩ Input Current ±1 µA max Typically ±30 nA Reference Range 1 to AVDD/2 V min/max Reference Output4 Enabled via CR8 in the AD5381 control register CR10 selects the reference voltage. Output Voltage 1.245/1.255 V min/max At ambient; optimized for 1.25 V operation; CR10 = 0 2.47/2.53 V min/max CR10 = 1 Reference TC ±10 ppm/°C max Temperature Range: +25°C to +85°C ±15 ppm/°C max Temperature Range: –40°C to +85°C Output Impedance 800 Ω typ OUTPUT CHARACTERISTICS3 Output Voltage Range2 0/AVDD V min/max Short-Circuit Current 40 mA max Load Current ±1 mA max Capacitive Load Stability RL = ∞ 200 pF max RL = 5 kΩ 1000 pF max DC Output Impedance 0.6 Ω max MONITOR PIN Output Impedance 1 kΩ typ Three-State Leakage Current 100 nA typ LOGIC INPUTS (EXCEPT SDA/SCL)3 DVDD = 2.7 V to 3.6 V VIH, Input High Voltage 2 V min VIL, Input Low Voltage DVDD > 3.6 0.8 V max DVDD ≤ 3.6 0.6 V max Input Current ±1 µA max Total for all pins; TA = TMIN to TMAX Pin Capacitance 10 pF max LOGIC INPUTS (SDA, SCL ONLY)3 VIH, Input High Voltage 0.7 × DVDD V min SMBus compatible at DVDD < 3.6 V VIL, Input Low Voltage 0.3 × DVDD V max SMBus compatible at DVDD < 3.6 V IIN, Input Leakage Current ±1 µA max VHYST, Input Hysteresis 0.05 × DVDD V min CIN, Input Capacitance 8 pF typ Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns Rev. E | Page 7 of 40 Document Outline Features Integrated Functions Applications Functional Block Diagram Table Of Contents Revision History General Description Specifications AD5381-5 Specifications AD5381-3 Specifications AC Characteristics Timing Characteristics Serial Interface Timing I2C Serial Interface Timing Parallel Interface Timing Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Control Register Contents Channel Monitor Function Hardware Functions Reset Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down Interfaces DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer START and STOP Conditions Repeated START Conditions Acknowledge Bit (ACK) AD5381 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pin A5 to Pin A0 Pin DB11 to Pin DB0 Microprocessor Interfacing Parallel Interface AD5381 to MC68HC11 AD5381 to PIC16C6x/7x AD5381 to 8051 AD5381 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit Monitor Function Toggle Mode Function Thermal Monitor Function Optical Attenuators Utilizing FIFO Outline Dimensions Ordering Guide