Datasheet AD5380 (Analog Devices) - 2

AD5380* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE MATERIALS
View a parametric search of comparable parts.
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
EVALUATION KITS Technical Articles
• AD5380 Evaluation Board • Software Calibration Reduces D/A Converter Offset and Gain Errors
DOCUMENTATION Application Notes DESIGN RESOURCES
• AN-1222: 40 Channels of Programmable Voltage with • AD5380 Material Declaration Excellent Temperature Drift Performance Using the • PCN-PDN Information AD5380 DAC • Quality And Reliability • AN-1223: Output Channel Monitoring Using the AD5380 • Symbols and Footprints Multichannel DAC
Data Sheet DISCUSSIONS
• AD5380:40-Channel, 3 V/5 V, Single-Supply, 14-Bit, denseDAC Data Sheet View all AD5380 EngineerZone Discussions.
Product Highlight SAMPLE AND BUY
• Extending the denseDAC™ Multichannel D/As Visit the product page to see pricing options.
User Guides
• UG-757: Evaluating the AD5380/AD5382 40-/32-Channel,
TECHNICAL SUPPORT
14-Bit Voltage Output DACs with On-Chip Reference Submit a technical question or find your regional support
SOFTWARE AND SYSTEMS REQUIREMENTS
number. • AD5380 IIO Multi-Channel DAC Linux Driver
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
Document Outline Features Integrated Functions Applications Functional Block Diagram Table Of Contents Revision History General Description Specifications AD5380-5 Specifications AD5380-3 Specifications AC Characteristics Timing Characteristics Serial Interface I2C Serial Interface Parallel Interface Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Control Register Contents Channel Monitor Function Hardware Functions RESET\ Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down AD5380 Interfaces DSP-, SPI-, Microwire-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer START and STOP Conditions Repeated START Conditions Acknowledge Bit (ACK) AD5380 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pins A5 to A0 Pins DB13 to DB0 Microprocessor Interfacing Parallel Interface AD5380 to MC68HC11 AD5380 to PIC16C6x/7x AD5380 to 8051 AD5380 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit AD5380 Monitor Function Toggle Mode Function Thermal Monitor Function AD5380 in a MEMS Based Optical Switch Optical Attenuators Utilizing the AD5380 FIFO Outline Dimensions Ordering Guide