Datasheet AD558 (Analog Devices) - 8

AD558 OUTPUT ADDRESS BUS AMP 0.5mA 16 V 16 OUT 16 –V ADDRESS SELECT 15 VOUT SENSE PULSE LOGIC 8080A 14 VOUT SELECT CS VOUT AD558 MEMW CE 13 AGND DB0–DB7
b. 0 V to 10 V Output Range
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Figure 11. Offset Connection Diagrams
8 DATA BUS INTERFACING THE AD558 TO MICROPROCESSOR MEMW
→
CE DATA BUSES DECODED ADDRESS SELECT PULSE
→
CS
The AD558 is configured to act like a “write only” location in b. 8080A/AD558 Interface memory that may be made to coincide with a read only memory location or with a RAM location. The latter case allows data
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previously written into the DAC to be read back later via the
ADDRESS BUS
RAM. Address decoding is partially complete for either ROM or RAM. Figure 12 shows interfaces for three popular micropro-
MA 0 – 7 8
cessor systems.
ADDRESS CS TPA LATCH & ADDRESS BUS 1802 AD558 VOUT DECODE MWR CE 16 16 DB0–DB7 ADDRESS 6800 DECODER 8 8 VMA V CS OUT DATA BUS AD558
φ
2 CDP 1802: MWR
→
CE DECODED ADDRESS SELECT PULSE
→
CS CE R/W DB0–DB7
c. 1802/AD558 Interface
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Figure 12. Interfacing the AD558 to Microprocessors
8 DATA BUS R/W
→
CE GATED DECODED ADDRESS
→
CS
a. 6800/AD558 Interface
Performance (typical @ +25
8
C, VCC
6
+5 V to +15 V unless otherwise noted) LSB 1.75 1.50 1.25 ALL AD558 LSB ALL AD558 1.00 AD558S, T 1/2 AD558S, T 0.75 ZERO ERROR 0.50 1/4 0.25 FULL 0 0 SCALE –0.25 o ERROR –55 –25 0 +25 +50 +75 +100 +125 C –0.50 –1/4 –0.75 –1.00 –1/2 1LSB = 0.39% OF FULL SCALE o –55 –25 0 +25 +50 +75 +100 +125 C 1LSB = 0.39% OF FULL SCALE
Figure 13. Full-Scale Accuracy vs. Temperature Figure 14. Zero Drift vs. Temperature Performance Performance of AD558 of AD558 REV. B –7–