Datasheet AD8139 (Analog Devices)

制造商Analog Devices
描述Low Noise, Rail-to-Rail, Differential ADC Driver
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修订版C
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Low Noise, Rail-to-Rail,. Differential ADC Driver. Data Sheet. AD8139. FEATURES. FUNCTIONAL BLOCK DIAGRAMS. Fully differential

Datasheet AD8139 Analog Devices, 修订版: C

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Low Noise, Rail-to-Rail, Differential ADC Driver Data Sheet AD8139 FEATURES FUNCTIONAL BLOCK DIAGRAMS Fully differential AD8139 Low noise –IN 1 8 +IN 2.25 nV/√Hz VOCM 2 7 NIC 2.1 pA/√Hz V+ 3 6 V– +OUT 4 5 –OUT Low harmonic distortion
001
98 dBc SFDR at 1 MHz NIC = NO INTERNAL CONNECTION.
04679-
85 dBc SFDR at 5 MHz
Figure 1. 8-Lead SOIC
72 dBc SFDR at 20 MHz AD8139 High speed TOP VIEW (Not to Scale) 410 MHz, 3 dB BW (G = 1) –IN 1 8 +IN 800 V/µs slew rate VOCM 2 7 NIC 45 ns settling time to 0.01% V+ 3 6 V– 69 dB output balance at 1 MHz +OUT 4 5 –OUT 80 dB dc CMRR
102
NIC = NO INTERNAL CONNECTION. Low offset: ±0.5 mV maximum
04679- Figure 2. 8-Lead LFCSP
Low input offset current: 0.5 µA maximum Differential input and output Differential-to-differential or single-ended-to-differential operation Rail-to-rail output Adjustable output common-mode voltage Wide supply voltage range: 5 V to 12 V Available in a small SOIC package and an 8-lead LFCSP
The AD8139 is manufactured on the proprietary Analog Devices,
APPLICATIONS
Inc., second-generation XFCB process, enabling it to achieve low
ADC drivers to 18 bits
levels of distortion with input voltage noise of only 2.25 nV/√Hz.
Single-ended-to-differential converters
The AD8139 is available in an 8-lead SOIC package with an
Differential filters
exposed paddle (EP) on the underside of its body and a 3 mm ×
Level shifters
3 mm LFCSP. It is rated to operate over the temperature range
Differential PCB drivers
of −40°C to +125°C.
Differential cable drivers 100 GENERAL DESCRIPTION )
The AD8139 is an ultralow noise, high performance differential
z / H
amplifier with rail-to-rail output. With its low noise, high
nV (
SFDR, and wide bandwidth, it is an ideal choice for driving
E
analog-to-digital converters (ADCs) with resolutions to 18 bits.
OIS N 10
The AD8139 is easy to apply, and its internal common-mode
GE
feedback architecture allows its output common-mode voltage
OLTA
to be controlled by the voltage applied to one pin. The internal
T V U
feedback loop also provides outstanding output balance as well
P IN
as suppression of even-order harmonic distortion products. Ful y differential and single-ended-to-differential gain configurations
1
are easily realized by the AD8139. Simple external feedback
10 100 1k 10k 100k 1M 10M 100M 1G
078
FREQUENCY (Hz)
networks consisting of four resistors determine the closed-loop 04679- gain of the amplifier. Figure 3. Input Voltage Noise vs. Frequency
Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS VS = ±5 V, VOCM = 0 V VS = 5 V, VOCM = 2.5 V ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Maximum Power Dissipation ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION TYPICAL CONNECTION AND DEFINITION OF TERMS Output Balance APPLICATIONS INFORMATION ESTIMATING NOISE, GAIN, AND BANDWIDTH WITH MATCHED FEEDBACK NETWORKS Estimating Output Noise Voltage Voltage Gain Feedback Factor Notation Input Common-Mode Voltage Calculating Input Impedance Input Common-Mode Swing Considerations Bandwidth vs. Closed-Loop Gain Estimating DC Errors Other Impact of Mismatches in the Feedback Networks Driving a Capacitive Load Layout Considerations Terminating a Single-Ended Input Exposed Paddle (EP) OUTLINE DIMENSIONS ORDERING GUIDE