Datasheet AD8137 (Analog Devices) - 10

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Data Sheet AD8137 ABSOLUTE MAXIMUM RATINGS Table 4.
The power dissipated in the package (PD) is the sum of the
Parameter Rating
quiescent power dissipation and the power dissipated in the Supply Voltage 12 V package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V V S) times the OCM VS+ to VS− quiescent current (I Power Dissipation See Figure 3 S). The load current consists of differential and common-mode currents flowing to the load, as well as Input Common-Mode Voltage VS+ to VS− currents flowing through the external feedback networks and Storage Temperature Range −65°C to +125°C the internal common-mode feedback loop. The internal resistor Operating Temperature Range −40°C to +125°C tap used in the common-mode feedback loop places a 1 kΩ Lead Temperature (Soldering, 10 sec) 300°C differential load on the output. RMS output voltages should be Junction Temperature 150°C considered when dealing with ac signals. Stresses above those listed under Absolute Maximum Ratings Airflow reduces θJA. In addition, more metal directly in contact may cause permanent damage to the device. This is a stress with the package leads from metal traces, through holes, ground, rating only; functional operation of the device at these or any and power planes reduces the θJA. other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute Figure 3 shows the maximum safe power dissipation in the maximum rating conditions for extended periods may affect package vs. the ambient temperature for the 8-lead SOIC device reliability. (125°C/W) and 8-lead LFCSP (θJA = 70°C/W) on a JEDEC standard 4-layer board. θJA values are approximations.
THERMAL RESISTANCE 3.0
θJA is specified for the worst-case conditions, that is, θJA is specified for the device soldered in a circuit board in still air.
2.5 Table 5. Thermal Resistance LFCSP 2.0 Package Type θJA θJC Unit
8-Lead SOIC/2-Layer 157 56 °C/W
1.5
8-Lead SOIC/4-Layer 125 56 °C/W 8-Lead LFCSP/4-Layer 70 56 °C/W
1.0 SOIC-8 MAXIMUM POWER DISSIPATION 0.5 MAXIMUM POWER DISSIPATION (W)
The maximum safe power dissipation in the AD8137 package
0
04771-0-022 is limited by the associated rise in junction temperature (TJ) on
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
the die. At approximately 150°C, which is the glass transition
AMBIENT TEMPERATURE (°C)
temperature, the plastic changes its properties. Even temporarily Figure 3. Maximum Power Dissipation vs. Ambient Temperature for a 4-Layer Board exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8137. Exceeding a junction temperature
ESD CAUTION
of 175°C for an extended period can result in changes in the silicon devices, potentially causing failure. Rev. E | Page 9 of 32 Document Outline Features Applications Functional Block Diagram General Descripton Revision History Specifications Absolute Maximum Ratings Thermal Resistance Maximum Power Dissipation ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Theory of Operation Applications Information Analyzing a Typical Application with Matched RF and RG Networks Typical Connection and Definition of Terms Output Balance Estimating Noise, Gain, and Bandwith with Matched Feedback Networks Estimating Output Noise Voltage and Bandwidth Voltage Gain Feedback Factor Notation Input Common-Mode Voltage Calculating Input Impedance Input Common-Mode Swing Considerations Bandwidth vs. Closed-Loop Gain Estimating DC Errors Additional Impact of Mismatches in the Feedback Networks Driving a Capacitive Load Layout Considerations Terminating a Single-Ended Input Power-Down Driving an ADC with Greater than 12-Bit Performance Outline Dimensions Ordering Guide Automotive Products