Datasheet AD8253 (Analog Devices) - 7

制造商Analog Devices
描述10 MHz, G = 1, 10, 100, 1000 iCMOS Programmable Gain Instrumentation Amplifier
页数 / 页25 / 7 — AD8253. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating. …
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AD8253. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating. 2.00. ) 1.75. W N (. 1.50. IO AT. MAXIMUM POWER DISSIPATION

AD8253 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3 Parameter Rating 2.00 ) 1.75 W N ( 1.50 IO AT MAXIMUM POWER DISSIPATION

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AD8253 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3.
power is the voltage between the supply pins (VS) times the quiescent current (I
Parameter Rating
S). Assuming the load (RL) is referenced to midsupply, the total drive power is V Supply Voltage ±17 V S/2 × IOUT, some of which is dissipated in the package and some of which is dissipated in the Power Dissipation See Figure 4 load (V Output Short-Circuit Current Indefinite1 OUT × IOUT). Common-Mode Input Voltage ±V The difference between the total drive power and the load S Differential Input Voltage ±V power is the drive power dissipated in the package. S Digital Logic Inputs ±VS PD = Quiescent Power + (Total Drive Power − Load Power) Storage Temperature Range –65°C to +125°C 2   Operating Temperature Range2 –40°C to +85°C V V V P  V  I     – D   S OUT OUT S S Lead Temperature (Soldering 10 sec) 300°C   2 R R  L  L Junction Temperature 140°C In single-supply operation with RL referenced to −VS, the worst θJA (4-Layer JEDEC Standard Board) 112°C/W case is VOUT = VS/2. Package Glass Transition Temperature 140°C Airflow increases heat dissipation, effectively reducing θJA. In 1 Assumes the load is referenced to midsupply. addition, more metal directly in contact with the package leads 2 Temperature for specified performance is −40°C to +85°C. For performance from metal traces through holes, ground, and power planes to +125°C, see the Typical Performance Characteristics section. reduces the θJA. Stresses above those listed under Absolute Maximum Ratings Figure 4 shows the maximum safe power dissipation in the may cause permanent damage to the device. This is a stress package vs. the ambient temperature on a 4-layer JEDEC rating only; functional operation of the device at these or any standard board. other conditions above those indicated in the operational
2.00
section of this specification is not implied. Exposure to absolute
) 1.75
maximum rating conditions for extended periods may affect
W N (
device reliability.
1.50 IO AT MAXIMUM POWER DISSIPATION IP 1.25 S S
The maximum safe power dissipation in the AD8253 package is
R DI 1.00 E
limited by the associated rise in junction temperature (TJ) on
W O 0.75
the die. The plastic encapsulating the die locally reaches the
P
junction temperature. At approximately 140°C, which is the
UM 0.50 IM
glass transition temperature, the plastic changes its properties.
AX M 0.25
Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently
0 –40 –20 0 20 40 60 80 100 120
04 0 shifting the parametric performance of the AD8253. Exceeding 3-
AMBIENT TEMPERATURE (°C)
98 a junction temperature of 140°C for an extended period can 06 Figure 4. Maximum Power Dissipation vs. Ambient Temperature result in changes in silicon devices, potentially causing failure.
ESD CAUTION
The still-air thermal properties of the package and PCB (θJA), the ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature is calculated as T  T  P  θ J A  D JA The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent Rev. B | Page 6 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ANALOG-TO-DIGITAL CONVERTER APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE