Datasheet AD8251 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | 10 MHz, G = 1, 2, 4, 8 iCMOS Programmable Gain Instrumentation Amplifier |
| 页数 / 页 | 25 / 1 — 10 MHz, 20 V/μs, G = 1, 2, 4, 8. CMOS. Programmable Gain Instrumentation … |
| 修订版 | B |
| 文件格式/大小 | PDF / 690 Kb |
| 文件语言 | 英语 |
10 MHz, 20 V/μs, G = 1, 2, 4, 8. CMOS. Programmable Gain Instrumentation Amplifier. AD8251. FEATURES. FUNCTIONAL BLOCK DIAGRAM
文件文字版本
link to page 1 link to page 1 link to page 1 link to page 1 link to page 1 link to page 1 link to page 1 link to page 1 link to page 1 link to page 1 link to page 1
10 MHz, 20 V/μs, G = 1, 2, 4, 8
i
CMOS Programmable Gain Instrumentation Amplifier AD8251 FEATURES FUNCTIONAL BLOCK DIAGRAM Small package: 10-lead MSOP DGND WR A1 A0 2 6 5 4 Programmable gains: 1, 2, 4, 8 LOGIC Digital or pin-programmable gain setting –IN 1 Wide supply: ±5 V to ±15 V Excellent dc performance High CMRR: 98 dB (minimum), G = 8 7 OUT Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.8 μV/°C (maximum), G = 8 Excellent ac performance +IN 10 Fast settling time: 785 ns to 0.001% (maximum) AD8251 High slew rate: 20 V/μs (minimum)
01
Low distortion: −110 dB THD at 1 kHz, 10 V swing 8 3 9
0 7-
+VS –VS REF
28
High CMRR over frequency: 80 dB to 50 kHz (minimum)
06 Figure 1.
Low noise: 18 nV/√Hz, G = 8 (maximum) Low power: 4.1 mA 25 APPLICATIONS 20 G = 8 Data acquisition 15 Biomedical analysis G = 4 Test and measurement ) B 10 d ( G = 2 GENERAL DESCRIPTION IN GA 5
The AD8251 is an instrumentation amplifier with digitally
G = 1
programmable gains that has GΩ input impedance, low output
0
noise, and low distortion, making it suitable for interfacing with
–5
sensors and driving high sample rate analog-to-digital converters 02 0 7- 28 (ADCs). It has a high bandwidth of 10 MHz, low THD of −110 dB,
–10
06
1k 10k 100k 1M 10M 100M
and fast settling time of 785 ns (maximum) to 0.001%. Offset
FREQUENCY (Hz)
drift and gain drift are guaranteed to 1.8 μV/°C and 10 ppm/°C, Figure 2. Gain vs. Frequency respectively, for G = 8. In addition to its wide input common voltage range, it boasts a high common-mode rejection of 80 dB
Table 1. Instrumentation Amplifiers by Category
at G = 1 from dc to 50 kHz. The combination of precision dc
General Mil Low High Speed
performance coupled with high speed capabilities makes the
Purpose Zero Drift Grade Power PGA
AD8251 an excellent candidate for data acquisition. Furthermore, AD82201 AD82311 AD620 AD6271 AD8250 AD8221 AD85531 AD621 AD6231 AD8251 this monolithic solution simplifies design and manufacturing AD8222 AD85551 AD524 AD82231 AD8253 and boosts performance of instrumentation by maintaining a AD82241 AD85561 AD526 tight match of internal resistors and amplifiers. AD8228 AD85571 AD624 The AD8251 user interface consists of a parallel port that allows 1 Rail-to-rail output. users to set the gain in one of two ways (see Figure 1). A 2-bit word The AD8251 is available in a 10-lead MSOP package and is sent via a bus can be latched using the WR input. An alternative is specified over the −40°C to +85°C temperature range, making it to use the transparent gain mode where the state of the logic an excellent solution for applications where size and packing levels at the gain port determines the gain. density are important considerations.
Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ADC APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE
10 MHz, 20 V/μs, G = 1, 2, 4, 8
i
CMOS Programmable Gain Instrumentation Amplifier AD8251 FEATURES FUNCTIONAL BLOCK DIAGRAM Small package: 10-lead MSOP DGND WR A1 A0 2 6 5 4 Programmable gains: 1, 2, 4, 8 LOGIC Digital or pin-programmable gain setting –IN 1 Wide supply: ±5 V to ±15 V Excellent dc performance High CMRR: 98 dB (minimum), G = 8 7 OUT Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.8 μV/°C (maximum), G = 8 Excellent ac performance +IN 10 Fast settling time: 785 ns to 0.001% (maximum) AD8251 High slew rate: 20 V/μs (minimum)
01
Low distortion: −110 dB THD at 1 kHz, 10 V swing 8 3 9
0 7-
+VS –VS REF
28
High CMRR over frequency: 80 dB to 50 kHz (minimum)
06 Figure 1.
Low noise: 18 nV/√Hz, G = 8 (maximum) Low power: 4.1 mA 25 APPLICATIONS 20 G = 8 Data acquisition 15 Biomedical analysis G = 4 Test and measurement ) B 10 d ( G = 2 GENERAL DESCRIPTION IN GA 5
The AD8251 is an instrumentation amplifier with digitally
G = 1
programmable gains that has GΩ input impedance, low output
0
noise, and low distortion, making it suitable for interfacing with
–5
sensors and driving high sample rate analog-to-digital converters 02 0 7- 28 (ADCs). It has a high bandwidth of 10 MHz, low THD of −110 dB,
–10
06
1k 10k 100k 1M 10M 100M
and fast settling time of 785 ns (maximum) to 0.001%. Offset
FREQUENCY (Hz)
drift and gain drift are guaranteed to 1.8 μV/°C and 10 ppm/°C, Figure 2. Gain vs. Frequency respectively, for G = 8. In addition to its wide input common voltage range, it boasts a high common-mode rejection of 80 dB
Table 1. Instrumentation Amplifiers by Category
at G = 1 from dc to 50 kHz. The combination of precision dc
General Mil Low High Speed
performance coupled with high speed capabilities makes the
Purpose Zero Drift Grade Power PGA
AD8251 an excellent candidate for data acquisition. Furthermore, AD82201 AD82311 AD620 AD6271 AD8250 AD8221 AD85531 AD621 AD6231 AD8251 this monolithic solution simplifies design and manufacturing AD8222 AD85551 AD524 AD82231 AD8253 and boosts performance of instrumentation by maintaining a AD82241 AD85561 AD526 tight match of internal resistors and amplifiers. AD8228 AD85571 AD624 The AD8251 user interface consists of a parallel port that allows 1 Rail-to-rail output. users to set the gain in one of two ways (see Figure 1). A 2-bit word The AD8251 is available in a 10-lead MSOP package and is sent via a bus can be latched using the WR input. An alternative is specified over the −40°C to +85°C temperature range, making it to use the transparent gain mode where the state of the logic an excellent solution for applications where size and packing levels at the gain port determines the gain. density are important considerations.
Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ADC APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE