Datasheet AD526 (Analog Devices) - 9

AD526 THEORY OF OPERATION TRANSPARENT MODE OF OPERATION
The AD526 is a complete software programmable gain amplifier In the transparent mode of operation, the AD526 will respond (SPGA) implemented monolithically with a drift-trimmed directly to level changes at the gain code inputs (A0, A1, A2) if BiFET amplifier, a laser wafer trimmed resistor network, JFET B is tied high and both CS and CLK are allowed to float low. analog switches and TTL compatible gain code latches. After the gain codes are changed, the AD526’s output voltage A particular gain is selected by applying the appropriate gain typically requires 5.5 µs to settle to within 0.01% of the final code (see Table I) to the control logic. The control logic turns value. Figures 26 to 29 show the performance of the AD526 for on the JFET switch that connects the correct tap on the gain positive gain code changes. network to the inverting input of the amplifier; all unselected JFET gain switches are off (open). The “on” resistance of the
A2
gain switches causes negligible gain error since only the
A1 A0
amplifier’s input bias current, which is less than 150 pA, actu-
+VS
ally flows through these switches.
+5V 0.1
m
F
The AD526 is capable of storing the gain code, (latched mode), B, A0, A1, A2, under the direction of control inputs CLK and
OUT
CS
16 15 14 13 12 11 10 9 FORCE
. Alternatively, the AD526 can respond directly to gain code changes if the control inputs are tied low (transparent mode).
A1 A0 CS CLK A2 B LOGIC AND LATCHES
For gains of 8 and 16, a fraction of the frequency compensation
16 8 4 2 1
capacitance (C1 in Figure 32) is automatically switched out of
VOUT
the circuit. This increases the amplifier’s bandwidth and im-
GAIN NETWORK
proves its signal settling time and slew rate.
– AD526 + 1 2 3 4 5 6 7 8 AMPLIFIER OUT SENSE +VS C1 0.1
m
F VIN –VS C2 VIN OUT
Figure 33. Transparent Mode
FORCE N1 N2 LATCHED MODE OF OPERATION
The latched mode of operation is shown in Figure 34. When
–V OUT S SENSE
either CS or CLK go to a Logic “1,” the gain code (A0, A1, A2, B) signals are latched into the registers and held until both CS
A0
and CLK return to “0.” Unused CS or CLK inputs should be tied
C O 14k
V to ground . The CS and CLK inputs are functionally and electri-
A1 N L T
cally equivalent.
G = 8 A R A2 T O 3.4k
V
C L RESISTOR TIMING SIGNAL NETWORK B H G = 2 E L A2 S O 1k
V
A1 CLK G I A0 G = 16 C +VS CS 1.7k
V
+5V 0.1
m
F G = 4 DIGITAL OUT GND 1k
V
1.7k
V
16 15 14 13 12 11 10 9 FORCE ANALOG ANALOG GND2 GND1 A1 A0 CS CLK A2 B
Figure 32. Simplified Schematic of the AD526
LOGIC AND LATCHES 16 8 4 2 1 VOUT GAIN NETWORK – AD526 + 1 2 3 4 5 6 7 8 OUT SENSE 0.1
m
F VIN –VS
Figure 34. Latched Mode –8– REV. D