Datasheet ADL5910 (Analog Devices) - 8

ADL5910 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS T IN– NBL V RS E Q 16 15 14 13 RFIN 1 12 Q DNC 2 11 GND ADL5910 TOP VIEW VCAL 3 10 DNC (Not to Scale) DECL 4 9 DNC 5 6 7 8 S S DNC DNC VPO VPO NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
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2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A LOW IMPEDANCE THERMAL AND ELECTRICAL GROUND PLANE.
13837- Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 RFIN RF Input. The RFIN pin is dc-coupled and is not internally matched. A broadband 50 Ω match is achieved using an external 82.5 Ω shunt resistor with a 0.47 µF ac coupling capacitor placed between the shunt resistor and the RF input. Smaller ac coupling capacitor values can be used if low frequency operation is not required. 2, 6, 8, 9, DNC Do Not Connect. Do not connect to these pins. 10 3 VCAL Threshold Calibration. The voltage on this pin determines the correct threshold voltage that must be applied to Pin 16 (VIN−) to set a particular RF power threshold. This process has two steps: first, measure the output voltage on VCAL with no RF signal applied to RFIN (this voltage is typically 750 mV). Next, apply the RF input power to RFIN, which causes the circuit to trip and again measure the voltage on the VCAL pin. The difference between these two voltages is equal to the threshold voltage that must be applied to VIN− during operation. 4 DECL Internal Decoupling. Bypass this pin to ground using a 4.02 Ω resistor connected in series with a 100 nF capacitor. 5, 7 VPOS Power Supply. The supply voltage range = 3.3 V ±10%. Place power supply decoupling capacitors on Pin 5. There is no requirement for power supply decoupling capacitors on Pin 7. 11 GND Device Ground. Connect the GND pin to system ground using a low impedance path. 12, 13 Q, Q Differential Digital Outputs of Threshold Detection Flip Flop. Q latches high when the output of the internal envelope detector exceeds the threshold voltage on the internal comparator VIN− input. 14 ENBL Device Enable. Connect the ENBL pin to logic high to enable the device. 15 RST Flip Flop Reset. Taking RST high clears the latched flip flop output, setting the Q and Q outputs to low and high, respectively. 16 VIN− Inverting Input to the Threshold Detection Comparator. The voltage on this pin is compared to the output voltage of the internal envelope detector, which is driven by the RF input level. If the output voltage of the envelope detector exceeds the voltage on VIN−, the flip flop latches the Q output to high and the Q output to low. EPAD Exposed Pad. Connect the exposed pad to a low impedance thermal and electrical ground plane. Rev. 0 | Page 8 of 22 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC CONNECTIONS Q AND QB RESPONSE TIME SETTING THE VIN− THRESHOLD DETECTION VOLTAGE APPLICATIONS INFORMATION A COMPLETE INPUT PROTECTION CIRCUIT RESET ON ENABLE OR AT POWER-UP IMPROVING FREQUENCY FLATNESS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE