Datasheet ADL5906 (Analog Devices) - 7

Data Sheet ADL5906 Parameter Test Conditions/Comments Min Typ Max Unit
5800 MHz ±1.0 dB Dynamic Range CW input, TA = 25°C 57 dB Maximum Input Level, ±1.0 dB Calibration at −50 dBm, −40 dBm, and 0 dBm 3 dBm Minimum Input Level, ±1.0 dB Calibration at −50 dBm, −40 dBm, and 0 dBm −54 dBm Deviation vs. Temperature Deviation from output at 25°C, VTADJ = 1 V −40°C < TA < +85°C; PIN = 0 dBm −2.4/+0 dB −40°C < TA < +85°C; PIN = −45 dBm −1.4/-0.2 dB −55°C < TA < +125°C; PIN = 0 dBm −3.6/+0 dB −55°C < TA < +125°C; PIN = −45 dBm −2.1/-0.2 dB Logarithmic Slope −65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm 42 mV/dB Logarithmic Intercept −65 dBm < PIN < +10 dBm; calibration at −40 dBm and 0 dBm −60 dBm OUTPUT INTERFACE VRMS (Pin 6) Output Swing, Control er Mode Swing range minimum, RL ≥ 500 Ω to ground 0.05 V Swing range maximum, RL ≥ 500 Ω to ground 3.92 V Current Source/Sink Capability 10/10 mA Rise Time PIN = off to −10 dBm, 10% to 90%, CRMS = 1 nF 0.1 µs Fall Time PIN = −10 dBm to off, 90% to 10%, CRMS = 1 nF 14.6 µs SETPOINT INPUT VSET (Pin 7) Voltage Range Log conformance error ≤ 1 dB, minimum 2.14 GHz 3.92 V Log conformance error ≤ 1 dB, maximum 2.14 GHz 0.4 V Input Resistance 72 kΩ Logarithmic Scale Factor f = 2.14 GHz 56 mV/dB Logarithmic Intercept f = 2.14 GHz −65 dBm TEMPERATURE COMPENSATION TADJ/PWDN (Pin 1) Input Voltage Range 0 VPOS V Input Bias Current VTADJ = 0.35 V 5 µA Input Resistance VTADJ = 0.35 V 70 kΩ VOLTAGE REFERENCE VREF (Pin 11) Output Voltage PIN = −55 dBm 2.3 V Temperature Sensitivity 25°C ≤ TA ≤ 125°C −0.12 mV/°C −55°C ≤ TA ≤ +25°C 0.07 mV/°C Short-Circuit Current Source/ 25°C ≤ TA ≤ 125°C 4/0.05 mA Sink Capability −55°C ≤ TA ≤ +25°C 3/0.05 mA Voltage Regulation TA = 25°C, ILOAD = 2 mA −0.4 % TEMPERATURE REFERENCE VTEMP (Pin 8) Output Voltage TA = 25°C, RL ≥ 10 kΩ 1.4 V Temperature Coefficient −40°C ≤ TA ≤ +125°C, RL ≥ 10 kΩ 4.8 mV/°C Short-Circuit Current Source/ 25°C ≤ TA ≤ 125°C 4/0.05 mA Sink Capability −55°C ≤ TA ≤ +25°C 3/0.05 mA Voltage Regulation TA = 25°C, ILOAD = 1 mA −2.8 % RMS TARGET INTERFACE VTGT (Pin 12) Input Voltage Range 0.2 2.5 V Input Bias Current VTGT = 0.8 V 8 µA Input Resistance 100 kΩ POWER-DOWN INTERFACE VTADJ/PWDN (Pin 1) Voltage Level to Enable VPWDN decreasing 1.3 V Voltage Level to Disable VPWDN increasing 1.4 V Input Bias Current VPWDN = 5 V 72 µA VPWDN = 0 V 0.1 µA Enable Time VPWDN low to VRMS, 10% to 90%, CRMS = 1 nF, PIN = 0 dBm 1.4 µs Disable Time VPWDN high to VRMS, 90% to 10%, CRMS = 1 nF, PIN = 0 dBm 1.0 µs Rev. A | Page 5 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Square Law Detector and Amplitude Target RF Input Interface Temperature Sensor Interface VREF Interface Temperature Compensation Interface Power-Down Interface VSET Interface Output Interface VTGT Interface Basis for Error Calculations Measurement Mode Basic Connections Setting VTADJ Setting VTGT Choosing a Value for CRMS Output Voltage Scaling System Calibration and Error Calculation Using VTEMP to Improve Intercept Temperature Drift Description of Characterization Evaluation Board Evaluation Board Assembly Drawings Outline Dimensions Ordering Guide