Datasheet ADL5502 (Analog Devices) - 7

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ADL5502 Parameter Test Conditions Min Typ Max Unit
VRMS OUTPUT Pin VRMS Maximum Output Voltage VS = 3.0 V, RLOAD ≥ 10 kΩ 2.4 V Output Offset No signal at RFIN 15 100 mV Pulse Response Time 10 dB step, 10% to 90% of settling level, no filter 15 μs capacitor Available Output Current 3 mA PEAK OUTPUT Pin PEAK Maximum Output Voltage VS = 3.0 V, RLOAD ≥ 10 kΩ 1.5 V Output Offset No signal at RFIN 14 100 mV Available Output Current 3 mA Envelope Modulation Bandwidth 5 10 MHz Peak Hold Time 1% voltage drop from last peak, CNTL = high 600 μs CONTROL INTERFACE Logic Level to Track Envelope, High 2.5 V ≤ VS ≤ 3.3 V, −40°C < TA < +85°C 1.8 VPOS V Input Current when High 2.5 V at CNTL, –40°C ≤ TA ≤ +85°C 0.05 0.1 μA Logic Level for Peak Hold Condition, Low 2.5 V ≤ VS ≤ 3.3 V, −40°C < TA < +85°C −0.5 +0.5 V Enable Time 0 dBm at RFIN, CNTL held high for >1 μs <0.1 μs ENABLE INTERFACE Pin ENBL Logic Level to Enable Power, High Condition 2.5 V ≤ VS ≤ 3.3 V, −40°C < TA < +85°C 1.8 VPOS V Input Current when High 2.5 V at ENBL, –40°C ≤ TA ≤ +85°C 0.05 0.1 μA Logic Level to Disable Power, Low Condition 2.5 V ≤ VS ≤ 3.3 V, −40°C < TA < +85°C −0.5 +0.5 V Power-Up Response Time4 CFLTR = open, 0 dBm at RFIN 12 μs CFLTR = 10 nF, 0 dBm at RFIN 10 μs POWER SUPPLIES Operating Range −40°C < TA < +85°C 2.5 3.3 V Quiescent Current No signal at RFIN,5 ENBL high input condition 3.0 mA Disable Current6 ENBL input low condition, CNTL in high condition <1 1 μA 1 Error referred to delta from 25°C response, see Figure 10, Figure 11, and Figure 12 for VRMS and Figure 16, Figure 17, and Figure 18 for PEAK. 2 Error referred to best-fit line at 25°C, see Figure 13, Figure 14, and Figure 15 for VRMS and Figure 19, Figure 20, and Figure 21 for PEAK. 3 Calculated using linear regression. 4 The response time is measured from 10% to 90% of settling level, see Figure 41, Figure 42, and Figure 43. 5 Supply current is input level dependant, see Figure 37. 6 Guaranteed but not tested; limits are specified at six sigma levels. Rev. A | Page 5 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION RMS CIRCUIT DESCRIPTION AND FILTERING FILTERING ENVELOPE PEAK-HOLD CIRCUIT OUTPUT BUFFERS MEASURING THE CREST FACTOR APPLICATIONS INFORMATION BASIC CONNECTIONS RF INPUT INTERFACING Resistive Tap RF Input Multiple RF Inputs LINEARITY Output Swing VRMS Output Offset OUTPUT DRIVE CAPABILITY AND BUFFERING SELECTING THE SQUARE-DOMAIN FILTER AND OUTPUT LOW-PASS FILTER POWER CONSUMPTION, ENABLE, AND POWER-ON/POWER-OFF RESPONSE TIME DEVICE CALIBRATION AND ERROR CALCULATION CALIBRATION FOR IMPROVED ACCURACY CALCULATION OF CREST FACTOR (CF) DRIFT OVER A REDUCED TEMPERATURE RANGE OPERATION AT HIGH FREQUENCIES DEVICE HANDLING EVALUATION BOARD Operating in Peak-Hold Mode Land Pattern and Soldering Information OUTLINE DIMENSIONS ORDERING GUIDE