Datasheet AD8364 (Analog Devices) - 9

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AD8364 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A A M M A CA M P EMP CHP DE CO VPSR ACO T ACO CL 24 23 22 21 20 19 18 17 VPSA 25 16 VSTA INHA 26 15 OUTA INLA 27 14 FBKA AD8364 PWDN 28 13 OUTP COMR 29 TOP VIEW 12 OUTN (Not to Scale) INLB 30 11 FBKB INHB 31 10 OUTB VPSB 32 9 VSTB 1 2 3 4 5 6 7 8 B B B CB EF VL M P CHP DE ADJB ADJA VR VL CL CO NOTES 1. THE EXPOSED PADDLE ON THE UNDERSIDE OF THE PACKAGE SHOULD BE SOLDERED TO
002
A GROUND PLANE WITH LOW THERMAL AND ELECTRICAL CHARACTERISTICS.
05334- Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description Equiv. Circuit
1 CHPB Connect to common via a capacitor to determine 3 dB point of Channel B input signal high-pass filter. 2, 23 DECB, DECA Decoupling Terminals for INHA/INLA and INHB/INLB. Connect to common via a large capacitance Figure 52 to complete input circuit. 3, 22, 29 COMB, COMA, COMR Input System Common Connection. Connect via low impedance to system common. 4, 5 ADJB, ADJA Temperature Compensation for Channel B and Channel A. An external voltage is connected to Figure 68 these pins to improve temperature drift. This voltage can be derived from VREF, that is, connect a resistor from VREF to ADJ[A, B] and another resistor from ADJ[A, B] to ground. The value of these resistors change as the frequency changes. 6 VREF General-Purpose Reference Voltage Output of 2.5 V. Figure 54 7 VLVL Reference Level Input for OUTP and OUTN. (Usually connected to VREF through a voltage divider Figure 58 or left open). 8, 17 CLPB, CLPA Channel B and Channel A Connection for Loop Filter Integration (Averaging) Capacitor. Connect a ground-referenced capacitor to this pin. A resistor can be connected in series with this capacitor to improve loop stability and response time. 9 VSTB The voltage applied to this pin sets the decibel value of the required RF input voltage to Channel Figure 56 B, which results in zero current flow in the loop integrating capacitor pin, CLPB. 10 OUTB Channel B Output of Error Amplifier. In measurement mode, normally connected directly to VSTB. Figure 57 11 FBKB Feedback Through 1 kΩ to the Negative Terminal of the Integrated Op Amp Driving OUTN. 12 OUTN Channel Differencing Op Amp Output. In measurement mode, normally connected directly to FBKB Figure 58 and fol ows the equation OUTN = OUTA − OUTB + VLVL. 13 OUTP Channel Differencing Op Amp Output. In measurement mode, normally connected directly to FBKA Figure 58 and fol ows the equation OUTP = OUTA − OUTB + VLVL. 14 FBKA Feedback Through 1kΩ to the Negative Terminal of the Integrated Op Amp Driving OUTP. 15 OUTA Channel A Output of Error Amplifier. In measurement mode, normally connected directly to VSTA. Figure 57 16 VSTA The voltage applied to this pin sets the decibel value of the required RF input voltage to Channel Figure 56 A that results in zero current flow in the loop integrating capacitor pin, CLPA. 18, 20 ACOM Analog Common for Channels A and B. Connect via low impedance to common. 21, 25, 32 VPSR, VPSA, VPSB Supply for the Input System of Channels A and B. Supply for the internal references. Connect to +5 V power supply. 19 TEMP Temperature Sensor Output. Figure 53 24 CHPA Connect to common via a capacitor to determine 3 dB point of Channel A input signal high-pass filter. 26, 27 INHA, INLA Channel A High and Low RF Signal Input Terminal. Figure 52 28 PWDN Disable/Enable Control Input. Apply logic high voltage to shut down the AD8364. Figure 55 30, 31 INLB, INHB Channel B Low and High RF Signal Input Terminal. Figure 52 Under Exposed Paddle The exposed paddle on the underside of the package must be soldered to a ground plane with Package low thermal and electrical characteristics. Rev. C | Page 8 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE OFFSET COMPENSATION TEMPERATURE SENSOR INTERFACE VREF INTERFACE POWER-DOWN INTERFACE VST[A, B] INTERFACE OUT[A, B, P, N] OUTPUTS MEASUREMENT CHANNEL DIFFERENCE OUTPUT USING OUT[P, N] CONTROLLER MODE RF MEASUREMENT MODE BASIC CONNECTIONS CONTROLLER MODE BASIC CONNECTIONS Automatic Power Control Automatic Gain Control CONSTANT OUTPUT POWER OPERATION GAIN-STABLE TRANSMITTER/RECEIVER TEMPERATURE COMPENSATION ADJUSTMENT DEVICE CALIBRATION AND ERROR CALCULATION SELECTING CALIBRATION POINTS TO IMPROVE ACCURACY OVER A REDUCED RANGE CHANNEL ISOLATION ALTERING THE SLOPE CHOOSING THE RIGHT VALUE FOR CHP[A, B] AND CLP[A, B] RF BURST RESPONSE TIME SINGLE-ENDED INPUT OPERATION PRINTED CIRCUIT BOARD CONSIDERATIONS PACKAGE CONSIDERATIONS DESCRIPTION OF CHARACTERIZATION BASIS FOR ERROR CALCULATIONS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE