Datasheet AD8362 (Analog Devices) - 28

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Data Sheet AD8362 OPERATION IN CONTROLLER MODE
To operate in controller mode, the link between VSET and The AD8362 provides a controller mode feature at the VOUT VOUT is broken. A setpoint voltage is applied to the VSET pin. Using VSET for the setpoint voltage, it is possible for the input, while VOUT is connected to the gain control terminal AD8362 to control subsystems such as power amplifiers (PAs), of the VGA, and the AD8362 RF input is connected to the out- VGAs, or variable voltage attenuators (VVAs), which have put of the VGA (generally using a directional coupler or power output power that decreases monotonically with respect to splitter and some additional attenuation). Based on the defined their (increasing) gain control signal. relationship between VOUT and the RF input signal when the device is in measurement mode, the AD8362 adjusts the voltage
CONTROLLED SYSTEM
on VOUT (VOUT is now an error amplifier output) until the
(OUTPUT POWER DECREASES AS VAPC INCREASES)
level at the RF input corresponds to the applied VSET. For
POUT OUTPUT INPUT P VAPC IN
example, in a closed loop system, if VSET is set to 3 V, VOUT
OUTPUT CONTROL VOLTAGE
increases or decreases until the input signal is equal to 0 dBm.
0.1V TO 4.9V
This relationship follows directly from the measurement mode
VS ATTN AD8362
transfer function (see Figure 10, Figure 11, and Figure 12).
1 COMM ACOM 16
Therefore, when the AD8362 operates in controller mode, there
C1 1:4 Z-RATIO C8 0.1µF 1000pF 2 CHPF VREF 15
is no defined relationship between VSET and VOUT. VOUT
C6 C4 3 DECL VTGT 14 1nF
settles to a value that results in balance between the input signal
C10 100pF C2 1000pF 4 INHI VPOS 13 1nF
levels appearing at INHI/INLO and VSET.
5 INLO VOUT 12 C7 SETPOINT C5
For this output power control loop to be stable, a ground-
1nF VOLTAGE 100pF 6 DECL VSET 11 T1 INPUT ETC1.6-4-2-3
referenced capacitor must be connected to the CLPF pin.
0V TO 3.5V 7 PWDN ACOM 10
This capacitor integrates the internal error current that is
8 COMM CLPF 9 C3
064 present when the loop is not balanced. 23-
(SEE TEXT)
029 Figure 64. Basic Connections for Controller Mode Operation Increasing VSET, which corresponds to demanding a higher signal from the VGA, tends to decrease VOUT. The VGA or VVA therefore must have a negative sense. In other words, increasing the gain control voltage decreases gain. If this is not the case, an op amp, configured as an inverter with suitable level shifting, can be used to correct the sense of the VOUT signal. Rev. F | Page 27 of 33 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION SETUP EQUIPMENT ANALYSIS CIRCUIT DESCRIPTION SQUARE LAW DETECTION VOLTAGE vs. POWER CALIBRATION OFFSET ELIMINATION TIME-DOMAIN RESPONSE OF THE CLOSED LOOP OPERATION IN RF MEASUREMENT MODE BASIC CONNECTIONS DEVICE DISABLE RECOMMENDED INPUT COUPLING Choosing Input Coupling Capacitors Single-Ended Input Drive OPERATION AT LOW FREQUENCIES CHOOSING A VALUE FOR CHPF CHOOSING A VALUE FOR CLPF ADJUSTING VTGT TO ACCOMMODATE SIGNALS WITH VERY HIGH CREST FACTORS ALTERING THE SLOPE TEMPERATURE COMPENSATION AND REDUCTION OF TRANSFER FUNCTION RIPPLE TEMPERATURE COMPENSATION AT VARIOUS WiMAX FREQUENCIES UP TO 3.8 GHz OPERATION IN CONTROLLER MODE RMS VOLTMETER WITH 90 dB DYNAMIC RANGE AD8362 EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE