Datasheet LTC6900 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | Low Power, 1kHz to 20MHz Resistor Set SOT-23 Oscillator |
| 页数 / 页 | 12 / 5 — PIN FUNCTIONS. V+ (Pin 1):. GND (Pin 2):. SET (Pin 3):. OUT (Pin 5):. DIV … |
| 文件格式/大小 | PDF / 164 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS. V+ (Pin 1):. GND (Pin 2):. SET (Pin 3):. OUT (Pin 5):. DIV (Pin 4):. BLOCK DIAGRAM
该数据表的模型线
文件文字版本
LTC6900
PIN FUNCTIONS V+ (Pin 1):
Voltage Supply (2.7V ≤ V+ ≤ 5.5V). This supply for the ÷1 setting, the highest frequency range. Floating must be kept free from noise and ripple. It should be by- Pin 4 divides the master oscillator by 10. Pin 4 should be passed directly to a ground plane with a 0.1μF capacitor. tied to V+ for the ÷100 setting, the lowest frequency range. To detect a fl oating DIV pin, the LTC6900 attempts to pull
GND (Pin 2):
Ground. Should be tied to a ground plane the pin toward midsupply. Therefore, driving the DIV pin for best performance. high requires sourcing approximately 2μA. Likewise, driv-
SET (Pin 3):
Frequency-Setting Resistor Input. The value ing DIV low requires sinking 2μA. When Pin 4 is fl oated, of the resistor connected between this pin and V+ deter- it should preferably be bypassed by a 1nF capacitor to mines the oscillator frequency. The voltage on this pin is ground or it should be surrounded by a ground shield to held by the LTC6900 to approximately 1.1V below the V+ prevent excessive coupling from other PCB traces. voltage. For best performance, use a precision metal fi lm
OUT (Pin 5):
Oscillator Output. This pin can drive 5kΩ and/ resistor with a value between 10kΩ and 2MΩ and limit or 10pF loads. Heavier loads may cause inaccuracies due the capacitance on this pin to less than 10pF. to supply bounce at high frequencies. Voltage transients,
DIV (Pin 4):
Divider-Setting Input. This three-state input coupled into Pin 5, above or below the LTC6900 power selects among three divider settings, determining the value supplies will not cause latchup if the current into/out of of N in the frequency equation. Pin 4 should be tied to GND the OUT pin is limited to 50mA.
BLOCK DIAGRAM
VRES = (V+ – VSET) = 1.1V TYPICALLY PROGRAMMABLE OUT DIVIDER (N) 5 V+ (÷1, 10 OR 100) 1 + V+ RSET GAIN = 1 I MASTER OSCILLATOR RES SET DIVIDER + 3 – I 2μA RES – ƒ SELECT MO = 10MHz • 20kΩ • (V+ – VSET) VBIAS THREE-STATE DIV 2 GND I 4 RES INPUT DETECT + 2μA – GND 6900 BD PATENT PENDING 6900fa 5
PIN FUNCTIONS V+ (Pin 1):
Voltage Supply (2.7V ≤ V+ ≤ 5.5V). This supply for the ÷1 setting, the highest frequency range. Floating must be kept free from noise and ripple. It should be by- Pin 4 divides the master oscillator by 10. Pin 4 should be passed directly to a ground plane with a 0.1μF capacitor. tied to V+ for the ÷100 setting, the lowest frequency range. To detect a fl oating DIV pin, the LTC6900 attempts to pull
GND (Pin 2):
Ground. Should be tied to a ground plane the pin toward midsupply. Therefore, driving the DIV pin for best performance. high requires sourcing approximately 2μA. Likewise, driv-
SET (Pin 3):
Frequency-Setting Resistor Input. The value ing DIV low requires sinking 2μA. When Pin 4 is fl oated, of the resistor connected between this pin and V+ deter- it should preferably be bypassed by a 1nF capacitor to mines the oscillator frequency. The voltage on this pin is ground or it should be surrounded by a ground shield to held by the LTC6900 to approximately 1.1V below the V+ prevent excessive coupling from other PCB traces. voltage. For best performance, use a precision metal fi lm
OUT (Pin 5):
Oscillator Output. This pin can drive 5kΩ and/ resistor with a value between 10kΩ and 2MΩ and limit or 10pF loads. Heavier loads may cause inaccuracies due the capacitance on this pin to less than 10pF. to supply bounce at high frequencies. Voltage transients,
DIV (Pin 4):
Divider-Setting Input. This three-state input coupled into Pin 5, above or below the LTC6900 power selects among three divider settings, determining the value supplies will not cause latchup if the current into/out of of N in the frequency equation. Pin 4 should be tied to GND the OUT pin is limited to 50mA.
BLOCK DIAGRAM
VRES = (V+ – VSET) = 1.1V TYPICALLY PROGRAMMABLE OUT DIVIDER (N) 5 V+ (÷1, 10 OR 100) 1 + V+ RSET GAIN = 1 I MASTER OSCILLATOR RES SET DIVIDER + 3 – I 2μA RES – ƒ SELECT MO = 10MHz • 20kΩ • (V+ – VSET) VBIAS THREE-STATE DIV 2 GND I 4 RES INPUT DETECT + 2μA – GND 6900 BD PATENT PENDING 6900fa 5