Datasheet LTC6902 (Analog Devices) - 8

LTC6902
U THEORY OF OPERATIO
As shown in the Block Diagram, the LTC6902’s master The master oscillator’s output is connected to the pro- oscillator is controlled by the ratio of the voltage between grammable divider. The output of the programmable the V+ and SET pins (V+ – VSET) and the current entering divider is then connected to the multiphase circuit with its the master oscillator, IMASTER. When the spread spectrum four outputs directly connected to output drivers. The final frequency modulation (SSFM) is disabled, IMASTER is output frequency is determined by the RSET resistor value, strictly determined by the V+ – VSET voltage and the ISET the programmable divider setting and the multiphase current. When SSFM is enabled, the current IMOD (modu- mode selected. The formula for setting the output fre- lation current) is subtracted from the ISET current to quency, fOUT, is below: determine the IMASTER current value. Here the IMASTER current is maximally at I MHz 10  k 20  SET but more often than not it is f = • Ω less than I OUT SET by a value determined by the IMOD value. In N • M  RSET  this way the frequency of the master oscillator is modu- lated to produce a frequency that is always less than or where: equal to the frequency set by the ISET current. 100 DIV Pin = + V The voltage on the SET pin is forced to approximately 1.1V  below V+ by the PMOS transistor and its gate bias voltage. N = 10 DIV Pin = Open   This voltage is accurate to ±8% at a particular input 1 DIV Pin = 0V  current and supply voltage (see Figure 2). The RSET 4 (4-Phase Output) PHPin = + V resistor, connected between the V+ and SET pins, locks  together the (V+ – V M = 3 (3 - H Phase Output) P Pin = Open  SET) voltage and the current ISET. This allows the parts to attain excellent frequency accuracy 1 (2- H Phase Output) P Pin = 0V  regardless of the precision of the SET pin voltage. The LTC6902 is optimized for use with RSET resistors between When the spread spectrum frequency modulation (SSFM) 10k and 2M. This corresponds to master oscillator fre- is disabled, the frequency fOUT is the final output fre- quencies between 100kHz and 20MHz. Additionally, the quency. When SSFM is enabled, fOUT is the maximum MOD pin’s voltage tracks the SET pin’s voltage. The RMOD output frequency with the RMOD resistor value determin- resistor connected between the V+ and MOD pins similarly ing the minimum output frequency. locks together the MOD pin voltage variation and the IMOD current to once more yield excellent accuracy. The programmable divider divides the master oscillator signal by 1, 10 or 100. The divide-by value is determined 1.4 by the state of the DIV input (Pin 2). Tie DIV to GND or drive it below 0.5V to select ÷1. This is the highest frequency 1.3 range, with the master output frequency passed directly to V+ = 5V 1.2 SET the multiphase circuit. The DIV pin may be floated or – V V+ = 3V + driven to midsupply to select ÷10, the intermediate fre- 1.1 = V quency range. The lowest frequency range, ÷100, is se- RESV 1.0 lected by tying DIV to V+ or driving it to within 0.4V of V+. Figure 3 shows the relationship between RSET, divider 0.9 setting and output frequency, including the overlapping 0.8 frequency ranges near 100kHz and 1MHz. 0.1 1 10 100 1000 IRES (µA) The multiphase circuit generates outputs that are either 69012 F02 2-, 3- or 4-phase waveforms. To generate the 3- and
Figure 2. V+ – VSET Variation with IRES
4-phase output signals, the output from the programmable 6902f 8