Datasheet LTC6905-XXX (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | Fixed Frequency SOT-23 Oscillator |
| 页数 / 页 | 8 / 5 — PI FU CTIO S. V+ (Pin 1):. GND (Pin 2):. OE (Pin 3):. OUT (Pin 5):. DIV … |
| 文件格式/大小 | PDF / 158 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. V+ (Pin 1):. GND (Pin 2):. OE (Pin 3):. OUT (Pin 5):. DIV (Pin 4):. BLOCK DIAGRA
该数据表的模型线
- LTC6905CS5-100#PBF LTC6905CS5-100#TRMPBF LTC6905CS5-100#TRMPBF LTC6905CS5-100#TRPBF LTC6905CS5-100#TRPBF LTC6905CS5-133#PBF LTC6905CS5-133#TRMPBF LTC6905CS5-133#TRMPBF LTC6905CS5-133#TRPBF LTC6905CS5-133#TRPBF LTC6905CS5-80#PBF LTC6905CS5-80#TRMPBF LTC6905CS5-80#TRMPBF LTC6905CS5-80#TRPBF LTC6905CS5-80#TRPBF LTC6905CS5-96#PBF LTC6905CS5-96#TRMPBF LTC6905CS5-96#TRMPBF LTC6905CS5-96#TRPBF LTC6905CS5-96#TRPBF LTC6905HS5-100#PBF LTC6905HS5-100#TRMPBF LTC6905HS5-100#TRMPBF LTC6905HS5-100#TRPBF LTC6905HS5-100#TRPBF LTC6905HS5-133#PBF LTC6905HS5-133#TRMPBF LTC6905HS5-133#TRMPBF LTC6905HS5-133#TRPBF LTC6905HS5-133#TRPBF LTC6905HS5-80#PBF LTC6905HS5-80#TRMPBF LTC6905HS5-80#TRMPBF LTC6905HS5-80#TRPBF LTC6905HS5-80#TRPBF LTC6905HS5-96#PBF LTC6905HS5-96#TRMPBF LTC6905HS5-96#TRMPBF LTC6905HS5-96#TRPBF LTC6905HS5-96#TRPBF LTC6905IS5-100#PBF LTC6905IS5-100#TRMPBF LTC6905IS5-100#TRMPBF LTC6905IS5-100#TRPBF LTC6905IS5-100#TRPBF LTC6905IS5-133#PBF LTC6905IS5-133#TRMPBF LTC6905IS5-133#TRMPBF LTC6905IS5-133#TRPBF LTC6905IS5-133#TRPBF LTC6905IS5-80#PBF LTC6905IS5-80#TRMPBF LTC6905IS5-80#TRMPBF LTC6905IS5-80#TRPBF LTC6905IS5-80#TRPBF LTC6905IS5-96#PBF LTC6905IS5-96#TRMPBF LTC6905IS5-96#TRMPBF LTC6905IS5-96#TRPBF LTC6905IS5-96#TRPBF
文件文字版本
LTC6905-XXX Series
U U U PI FU CTIO S V+ (Pin 1):
Voltage Supply (2.7V ≤ V+ ≤ 5.5V). This supply to V+ for the ÷1 setting, the highest frequency range. Float- must be kept free from noise and ripple. It should be ing Pin 4 divides the master oscillator by 2. Pin 4 should bypassed directly to the GND (Pin 2) with a 0.1µF capacitor be tied to GND for the ÷4 setting, the lowest frequency range. or higher. To detect a floating DIV pin, the LTC6905 attempts to pull the pin toward midsupply. This is realized with two internal
GND (Pin 2):
Ground. Should be tied to a ground plane for current sources, one tied to V+ and Pin 4 and the other one best performance. tied to ground and Pin 4. Therefore, driving the DIV pin high
OE (Pin 3):
Output Enable. Pull to V+ or leave floating to requires sourcing approximately 15µA. Likewise, driving enable the output driver (Pin 5). Pull low to disable the DIV low requires sinking 15µA. When Pin 4 is floated, it output. The output is disabled asynchronously. Pulling OE should be bypassed by a 1nF capacitor to ground or it should pin low will immediately disable the output. Pulling the OE be surrounded by a ground shield to prevent excessive cou- pin high will bring the output high on the next low to high pling from other PCB traces. transition of the clock. This eliminates pulse slivers.
OUT (Pin 5):
Oscillator Output. This pin can drive 5kΩ
DIV (Pin 4):
Divider-Setting Input. This three-state input and/or 5pF loads. For heavier loads, refer to the Applica- selects among three divider settings. Pin 4 should be tied tions Information section.
W BLOCK DIAGRA
3 OE VRES = 1V ±5% fMO f V+ (V+ – V PROGRAMMABLE OSC = SET) N OUT 1 DIVIDER 5 (N = 1, 2 OR 4) + R GAIN = 1 SET I MASTER OSCILLATOR RES – DIVIDER V+ SELECT fMO 15µA – DIV + THREE-STATE 4 – VBIAS INPUT DETECT IRES + 15µA 2 GND GND 6905x BD
Table 1. LTC6905-XXX Frequency Settings DIV SETTING LTC6905-133 LTC6905-100 LTC6905-96 LTC6905-80
V+ 133.33MHz 100MHz 96MHz 80MHz OPEN 66.66MHz 50MHz 48MHz 40MHz GND 33.33MHz 25MHz 24MHz 20MHz 6905xfa 5
U U U PI FU CTIO S V+ (Pin 1):
Voltage Supply (2.7V ≤ V+ ≤ 5.5V). This supply to V+ for the ÷1 setting, the highest frequency range. Float- must be kept free from noise and ripple. It should be ing Pin 4 divides the master oscillator by 2. Pin 4 should bypassed directly to the GND (Pin 2) with a 0.1µF capacitor be tied to GND for the ÷4 setting, the lowest frequency range. or higher. To detect a floating DIV pin, the LTC6905 attempts to pull the pin toward midsupply. This is realized with two internal
GND (Pin 2):
Ground. Should be tied to a ground plane for current sources, one tied to V+ and Pin 4 and the other one best performance. tied to ground and Pin 4. Therefore, driving the DIV pin high
OE (Pin 3):
Output Enable. Pull to V+ or leave floating to requires sourcing approximately 15µA. Likewise, driving enable the output driver (Pin 5). Pull low to disable the DIV low requires sinking 15µA. When Pin 4 is floated, it output. The output is disabled asynchronously. Pulling OE should be bypassed by a 1nF capacitor to ground or it should pin low will immediately disable the output. Pulling the OE be surrounded by a ground shield to prevent excessive cou- pin high will bring the output high on the next low to high pling from other PCB traces. transition of the clock. This eliminates pulse slivers.
OUT (Pin 5):
Oscillator Output. This pin can drive 5kΩ
DIV (Pin 4):
Divider-Setting Input. This three-state input and/or 5pF loads. For heavier loads, refer to the Applica- selects among three divider settings. Pin 4 should be tied tions Information section.
W BLOCK DIAGRA
3 OE VRES = 1V ±5% fMO f V+ (V+ – V PROGRAMMABLE OSC = SET) N OUT 1 DIVIDER 5 (N = 1, 2 OR 4) + R GAIN = 1 SET I MASTER OSCILLATOR RES – DIVIDER V+ SELECT fMO 15µA – DIV + THREE-STATE 4 – VBIAS INPUT DETECT IRES + 15µA 2 GND GND 6905x BD
Table 1. LTC6905-XXX Frequency Settings DIV SETTING LTC6905-133 LTC6905-100 LTC6905-96 LTC6905-80
V+ 133.33MHz 100MHz 96MHz 80MHz OPEN 66.66MHz 50MHz 48MHz 40MHz GND 33.33MHz 25MHz 24MHz 20MHz 6905xfa 5