Datasheet LTC6907 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Micropower, 40kHz to 4MHz Resistor Set Oscillator in SOT-23 |
| 页数 / 页 | 12 / 10 — APPLICATIO S I FOR ATIO. Alternative Methods for Setting the Output … |
| 文件格式/大小 | PDF / 175 Kb |
| 文件语言 | 英语 |
APPLICATIO S I FOR ATIO. Alternative Methods for Setting the Output Frequency. Figure 12. Current Controlled Oscillator
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LTC6907
U U W U APPLICATIO S I FOR ATIO Alternative Methods for Setting the Output Frequency
Figure 12 and Figure 13 show a current controlled oscilla- tor and a voltage controlled oscillator. These circuits are Any means of sinking current from the SET pin will control not highly accurate if used alone, but can be very useful if the output frequency of the LTC6907. Equation 2 (re- they are enclosed in an overall feedback circuit such as a peated below) gives the fundamental relationship between phase-locked loop. frequency and the SET pin voltage and current: 1 V t SET = = • pF OSC 5 (2) ƒ I OSC SET LTC6907 4MHz TO 400kHz V+ V+ OUT 0µA This equation shows that the LTC6907 converts conduc- GND GRD TO 11.25µA 10k tance (ISET/VSET) to frequency or, equivalently, converts DIV SET resistance (RSET = VSET/ISET) to period. 49.9k VSET is the voltage across an internal diode, and as such 6907 F12 it is given approximately by:
Figure 12. Current Controlled Oscillator
I V ≅ V •Log SET SET T e I LTC6907 S 4MHz TO 400kHz ⎛ V+ V+ OUT I ⎞ ≅ . 25 mV 9 • Log SET – . 2 mV 3 / C GND GRD e ⎝⎜ V 82 • – 10 18 A ⎠⎟ ° DIV SET CTRL R 0V TO 0.675V (VSET) SET 499k 56.2k where 6907 F13 VT = kT/q = 25.9mV at T = 300°K (27°C)
Figure 13. Voltage Controlled Oscillator
IS ≅ 82 • 10–18 Amps (IS is also temperature dependent)
Jitter and Divide Ratio
VSET varies with temperature and the SET pin current. The At a given output frequency, a higher master oscillator response of VSET to temperature is shown in the Typical frequency and a higher divide ratio will result in lower jitter Performance graphs. VSET changes approximately –2.3mV/ and higher power supply dissipation. Indeterminate jitter °C. At room temperature VSET increases 18mV/octave or percentage will decrease by a factor of slightly less than 60mV/decade of increase in ISET. the square root of the divider ratio, while determinate jitter If the SET pin is driven with a current source generating will not be similarly attenuated. Please consult the speci- ISET, the oscillator output frequency will be: fication tables for typical jitter at various divider ratios. SE I T pF 5 ƒ ≅ OSC ⎛ ⎞ SE I T 25. mV 9 •Loge ⎝⎜ – 2 3 . mV/ C ° 82 • 10 18 – A ⎠⎟ 6907fa 10
U U W U APPLICATIO S I FOR ATIO Alternative Methods for Setting the Output Frequency
Figure 12 and Figure 13 show a current controlled oscilla- tor and a voltage controlled oscillator. These circuits are Any means of sinking current from the SET pin will control not highly accurate if used alone, but can be very useful if the output frequency of the LTC6907. Equation 2 (re- they are enclosed in an overall feedback circuit such as a peated below) gives the fundamental relationship between phase-locked loop. frequency and the SET pin voltage and current: 1 V t SET = = • pF OSC 5 (2) ƒ I OSC SET LTC6907 4MHz TO 400kHz V+ V+ OUT 0µA This equation shows that the LTC6907 converts conduc- GND GRD TO 11.25µA 10k tance (ISET/VSET) to frequency or, equivalently, converts DIV SET resistance (RSET = VSET/ISET) to period. 49.9k VSET is the voltage across an internal diode, and as such 6907 F12 it is given approximately by:
Figure 12. Current Controlled Oscillator
I V ≅ V •Log SET SET T e I LTC6907 S 4MHz TO 400kHz ⎛ V+ V+ OUT I ⎞ ≅ . 25 mV 9 • Log SET – . 2 mV 3 / C GND GRD e ⎝⎜ V 82 • – 10 18 A ⎠⎟ ° DIV SET CTRL R 0V TO 0.675V (VSET) SET 499k 56.2k where 6907 F13 VT = kT/q = 25.9mV at T = 300°K (27°C)
Figure 13. Voltage Controlled Oscillator
IS ≅ 82 • 10–18 Amps (IS is also temperature dependent)
Jitter and Divide Ratio
VSET varies with temperature and the SET pin current. The At a given output frequency, a higher master oscillator response of VSET to temperature is shown in the Typical frequency and a higher divide ratio will result in lower jitter Performance graphs. VSET changes approximately –2.3mV/ and higher power supply dissipation. Indeterminate jitter °C. At room temperature VSET increases 18mV/octave or percentage will decrease by a factor of slightly less than 60mV/decade of increase in ISET. the square root of the divider ratio, while determinate jitter If the SET pin is driven with a current source generating will not be similarly attenuated. Please consult the speci- ISET, the oscillator output frequency will be: fication tables for typical jitter at various divider ratios. SE I T pF 5 ƒ ≅ OSC ⎛ ⎞ SE I T 25. mV 9 •Loge ⎝⎜ – 2 3 . mV/ C ° 82 • 10 18 – A ⎠⎟ 6907fa 10