Datasheet LTC6909 (Analog Devices) - 6

LTC6909
pin Functions V+A (Pin 1):
Analog Voltage Supply (2.7V ≤ V+A ≤ 5.5V). part’s internal frequency setting loop has settled, the out- This supply should be kept free of noise and ripple. It puts are active, clean and operating at the set frequency should be bypassed directly to GND with a 0.1µF or greater (first cycle accurate). low ESR capacitor. V+A and V+D must be connected to the
V+D (Pin 13):
Digital Voltage Supply (2.7V ≤ V+D ≤ 5.5V). same supply voltage. This pin should be bypassed directly to GND with a 0.1µF
GND (Pin 2):
Ground Connections. Should be tied to a or greater low ESR capacitor. V+D and V+A must be con- ground plane for best performance. nected to the same supply voltage.
PH0, PH1, PH2 (Pins 3, 4, 15):
Output Phasing Selec-
MOD (Pin 14):
Spread Spectrum Frequency Modulation tion Pins. These are standard CMOS logic input pins and Setting Input. This input selects among four modulation they do not have an internal pull-up or pull-down. These rate settings. The MOD pin should be tied to ground for pins must be connected to a valid logic input 0 or 1 volt- an fOUT/16 modulation rate. Floating the MOD pin selects age. Connect the pins to GND for a logic 0 and to the V+D an fOUT/32 modulation rate. The MOD pin should be tied pin for a logic 1. These pins configure the output phase to V+D for the fOUT/64 modulation rate. Tying one of the relationships as follows: active outputs to the MOD pin turns the modulation off. To detect a floating MOD pin, the LTC6909 attempts to
PH2 PH1 PH0 MODE
pull the pin to the midsupply point. This is realized with 0 0 0 All Outputs Are Floating (Hi-Z) two internal current sources, one tied to V+D and MOD 0 0 1 All Outputs Are Held Low and the other one tied to GND and MOD. Therefore, driv- 0 1 0 3-Phase Mode (PH = 3) ing the MOD pin high requires sourcing approximately 0 1 1 4-Phase Mode (PH = 4) 2µA. Likewise, driving the MOD pin low requires sinking 1 0 0 5-Phase Mode (PH = 5) approximately 2µA.
When the MOD pin is floated for the
1 0 1 6-Phase Mode (PH = 6)
fOUT/32 modulation rate, it must be bypassed using a
1 1 0 7-Phase Mode (PH = 7)
1nF or larger, capacitor to GND.
Any AC signal coupling 1 1 1 8-Phase Mode (PH = 8) to the MOD pin could potentially be detected and stop the frequency modulation. The PH0, PH1, PH2 pin connections not only determine the phase relationship of the output signals but also divide
SET (Pin 16):
Frequency Setting Resistor Input. The value the master oscillator frequency by the value PH. of the resistor connected between this pin and V+A deter- mines the frequency of the master oscillator. The output
OUT1 Through OUT8 (Pins 5 Through 12):
Oscillator frequency, f Outputs. These are CMOS rail-to-rail logic outputs with OUT, is the master oscillator frequency divided by PH as set by the PH0, PH1 and PH2 pin connections. a series resistance of approximately 40Ω, capable of The voltage on this pin is held approximately 1.1V below driving 1k and/or 50pF loads. Larger loads may cause V+A. For best performance, use a precision metal film minor frequency inaccuracies due to supply bounce at resistor with a value between 20k and 400k, and limit the high frequencies. When any output pin is not in use, it is capacitance on the pin to less than 10pF. Resistor values in a floating, high impedance state. The outputs are also outside of this range will have some loss of accuracy as held in a high impedance state during start-up. After the noted in the Electrical Characteristics table. 6909fa 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts