Datasheet LTC6909 (Analog Devices) - 8

LTC6909
operAtion
As shown in the Block Diagram, the LTC6909’s master When the spread spectrum frequency modulation (SSFM) oscillator is controlled by the ratio of the voltage between is disabled, the master oscillator frequency is stationary. the V+A and SET pins and the current entering the SET pin When SSFM is enabled, the master oscillator frequency (IMASTER). When the spread spectrum frequency modula- varies from 0.9 • fMASTER to 1.1 • fMASTER. tion (SSFM) is disabled, IMASTER is strictly determined by the (V+A – VSET) voltage and the RSET resistor. When SSFM
Output Frequency and Configurations
is enabled, IMASTER is modulated by a filtered pseudoran- The output frequency of the LTC6909 is set by the R dom noise (PRN) signal. Here the I SET MASTER current is a resistor value and the connections of the PH0, PH1 and random value uniformly distributed between (ISET – 10%) PH2 logic input pins. The following formula defines the and (ISET + 10%). In this way, the frequency is modulated relationship: to produce an approximately flat frequency spectrum, centered about the set frequency with a bandwidth equal fOUT = 20MHz • 10k/(RSET • PH) to approximately 20% of the center frequency. where PH = 3, 4, 5, 6, 7 or 8 and is defined as follows: The voltage on the SET pin is forced to approximately 1.1V
PH2 PH1 PH0 MODE
below V+A by the PMOS transistor and its gate bias volt- 0 0 0 All Outputs Are Floating (Hi-Z) age. This voltage is accurate to ±5% at a particular input 0 0 1 All Outputs Are Held Low current and supply voltage (see Figure 1). The LTC6909 0 1 0 3-Phase Mode (PH = 3) is optimized for use with resistors between 20k and 400k 0 1 1 4-Phase Mode (PH = 4) corresponding to master oscillator frequencies between 1 0 0 5-Phase Mode (PH = 5) 500kHz and 10MHz. Accurate master oscillator frequen- 1 0 1 6-Phase Mode (PH = 6) cies up to 20MHz (RSET = 10k) are attainable if the supply 1 1 0 7-Phase Mode (PH = 7) voltage is greater than 4V. The RSET resistor, connected between the V+A and SET pins, locks together the (V+A – 1 1 1 8-Phase Mode (PH = 8) VSET) voltage and the current ISET. This allows the parts The PH0, PH1 and PH2 pins are standard logic input pins. to attain excellent frequency accuracy regardless of the These pins do not have any active pull-up or pull-down precision of the SET pin. The master oscillation frequency is: circuitry. As such, they cannot be left floating and must be fMASTER = 20MHz • 10k/RSET connected to a valid logic high or low voltage. The PH0, PH1 and PH2 pin connections not only divide the master 1.4 oscillator frequency by the value PH but also determine TA = 25°C the phase relationship between the output signals. Figure 1.3 2 shows the output waveforms for each of the eight pos- 1.2 sible output configurations. SET V+ = 5V + – V 1.1 Note that 2-phase, complementary (180° phase shifted) = V V+ = 3V outputs are available in the 4-, 6- and 8-phase modes V RES 1.0 by choosing the correct pair of signals. For example, in 4-phase mode, OUT1 and OUT3 (or OUT2 and OUT4) are 0.9 complementary. 0.80.1 1 10 100 1000 IRES (µA) 6909 F01
Figure 1. V+ – VSET Variation with IRES
6909fa 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts