Datasheet LTC6930-X.XX (Analog Devices) - 8

LTC6930-X.XX
pin FuncTions V+ (Pins 1, 8):
Positive Supply Pins. Each supply pin
OUT (Pin 7):
Oscillator Output. Drives up to 50pF capaci- should be bypassed directly to the neighboring GND pin tive or 1k resistive load (Refer to Supply Current vs Load with a 0.1µF ceramic capacitor, and must be externally Capacitance in Typical Performance Characteristics sec- connected to the other V+ pin (see recommended layout). tion). Typical series resistance is less than 80Ω at 1.7V
GND (Pins 2, 6):
Ground Pins. Each should be connected and less than 40Ω at 3V supply. The output trace should to a low inductance ground plane and must be connected be isolated as much as possible from Pin 1 and Pin 2. to the other GND pin and on the DFN package, Pin 9. The OUT pin is held low during start-up, and remains free from glitches and runt pulses during DIV pin switching.
DIVA, DIVB, DIVC (Pins 3, 4, 5):
Output Prescaler. Se- lects divide ratio of master oscillator frequency used to
Exposed Pad (Pin 9, DFN Only):
The Exposed Pad must generate the output. See frequency setting Table 1 for be soldered to a PCB plane connected to GND. function. These are standard CMOS logic inputs with a typical threshold of 1.25V
applicaTions inForMaTion Theory of Operation Output Driver and Loading
The LTC6930 is an entirely self contained all silicon oscil- The output of the LTC6930 is a low series resistance 40Ω lator which consists of a master oscillator, a control loop CMOS driver with controlled rise/fall times to limit RF and an output frequency divider. The master oscillator interference and power supply spikes generated by the operates between 4.2MHz and 8.2MHz and is factory output while preserving the ability to drive low impedance programmed. The master oscillator frequency is accurately loads. Especially at high frequencies, the capacitive loading maintained over temperature and environmental extremes of the output of the LTC6930 may cause the majority of by a proprietary switched capacitor feedback loop. the power supply dissipation of the part. Each LTC6930 oscillator has an output frequency divider The LTC6930 supply current is specified at an output load which is controlled via the DIVA, DIVB and DIVC inputs. of 5pF, which is equivalent to two standard HC logic inputs. The divider divides the master frequency by 2N, where N The portion of the power supply current needed to drive is an integer from 0 to 7 (divider ranges from 1 to 128). a capacitive load may be calculated as: See Table 1 for the full range of frequencies covered by I the LTC6930 family. SUPPLY = CLOAD • VSWING • fOSC where C The presence of two sets of supply pins and careful internal LOAD is the 5pF load capacitance, VSWING is the voltage swing, in this case up to 5.5V, and f layout reduce interference between the oscillator output OSC is the fre- quency of the oscillator output. Driving a 5.5V swing into a and the control loop. This allows the LTC6930 to provide 5pF load at 8MHz takes an average of 220µA. To calculate a clean output frequency with very little deterministic jitter, the portion of the supply current needed for a 50pF load, even in cases of heavy output loading and noisy operating simply substitute 50pF for C environments. LOAD in the same equation: 50pF • 5.5V • 8MHz = 2.2mA The supply voltage of the LTC6930 is internally regulated to maintain a very low frequency drift over supply. The majority of this power is expended during the rise and fall time of the output signal, not while it is in a steady 6930fe 8 For more information www.linear.com/LTC6930 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information AC Electrical Characteristics DC Electrical Characteristics Timing Characteristics Pin Functions Applications Information Package Description Revision History Related Parts